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* Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
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* Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
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* Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-072-26/+22
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-022-31/+64
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+1
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* Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0814-15/+15
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* sim: Add wide port support.Marcelina Kościelnicka2021-05-251-3/+3
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* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-1/+1
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* sim: Avoid a crash on empty cell connection.Marcelina Kościelnicka2021-03-081-1/+1
| | | | Fixes #2513.
* assertpmux: Fix crash on unused $pmux output.Marcelina Kościelnicka2021-02-221-1/+1
| | | | Fixes #2595.
* Add #include needed to build with gcc-11Gabriel Somlo2020-11-261-0/+1
| | | | Suggested by Jeff Law <law@redhat.com>
* Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
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* Merge pull request #2403 from nakengelhardt/sim_timescaleN. Engelhardt2020-10-221-0/+21
|\ | | | | sim -vcd: add date, version, and option for timescale
| * use strftime instead of put_time for gcc 4.8 compatibilityN. Engelhardt2020-10-211-4/+5
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| * wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
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| * sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
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* | sim: Use Mem helper.Marcelina Kościelnicka2020-10-211-103/+90
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* | clk2fflogic: Use Mem helper.Marcelina Kościelnicka2020-10-211-68/+45
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* use the new isPublic() in a few placesN. Engelhardt2020-09-142-4/+4
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* async2sync: Support all FF types.Marcelina Kościelnicka2020-07-302-145/+162
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* async2sync: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-53/+11
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* clk2fflogic: Support all FF types.Marcelina Kościelnicka2020-07-241-200/+122
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* qbfsat: Add `-solver-option` option.Alberto Gonzalez2020-07-202-1/+15
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* clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-091-57/+51
| | | | | | | This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* Merge pull request #2208 from boqwxp/qbfsat-cleanupclairexen2020-07-022-255/+273
|\ | | | | qbfsat: Cleanup and refactoring
| * qbfsat: Remove useless comment and #ifndef guards.Alberto Gonzalez2020-07-011-5/+0
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| * qbfsat: Specify default values for some options in the help message.Alberto Gonzalez2020-07-011-0/+2
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| * qbfsat: Clean up external executable command lines and update temporary ↵Alberto Gonzalez2020-07-011-3/+7
| | | | | | | | directory name.
| * qbfsat: Clean up and refactor data structures into `qbfsat.h`.Alberto Gonzalez2020-07-012-248/+265
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* | Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ffclairexen2020-07-021-2/+1
|\ \ | |/ |/| fmcombine: use the master ff cell type list
| * fmcombine: use the master ff cell type listMarcelina Kościelnicka2020-06-301-2/+1
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* | Merge pull request #2138 from boqwxp/qbfsat-oflagclairexen2020-07-011-16/+47
|\ \ | | | | | | qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
| * | qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.Alberto Gonzalez2020-06-301-16/+47
| |/ | | | | | | | | | | Thanks to @mwk for the gate mapping part of the ABC scripts. Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
* | Merge pull request #2206 from boqwxp/qbfsat-fix-name-specializationclairexen2020-07-011-2/+24
|\ \ | | | | | | qbfsat: Fix name-based hole specialization
| * | qbfsat: Fix name-based hole specialization.Alberto Gonzalez2020-06-301-2/+24
| |/ | | | | | | Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
* | Merge pull request #2199 from YosysHQ/mmicko/sim_memoryclairexen2020-06-301-1/+4
|\ \ | |/ |/| sim - error when memrd and memwr detected
| * sim - error when memrd and memwr detectedMiodrag Milanovic2020-06-291-1/+4
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* | Give error that options are exclusiveMiodrag Milanovic2020-06-291-2/+6
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* | cleanupMiodrag Milanovic2020-06-291-12/+13
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* | expose pass fixMiodrag Milanovic2020-06-291-5/+16
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* log, qbfsat: Include child process time in `PerformanceTimer::query()` and ↵Alberto Gonzalez2020-06-211-1/+6
| | | | report the time for each call to the QBF-SAT solver.
* qbfsat: Simplify solution recovery parsing and tweak the solution regexes.Alberto Gonzalez2020-06-211-22/+12
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* qbfsat: Avoid instantiating `AttrObject`s directly.Alberto Gonzalez2020-06-211-9/+6
| | | | Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
* qbfsat: Simplify solution format and replace `SigBit::str()` with ↵Alberto Gonzalez2020-06-211-19/+37
| | | | | | `log_signal()`. Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
* qbfsat: Fixes three bugs.Alberto Gonzalez2020-06-211-5/+17
| | | | | | 1. Infinite loop in the optimization procedure when the first solution found while maximizing is at zero. 2. A signed-ness issue when maximizing. 3. Erroneously entering bisection mode with no wire to optimize.
* qbfsat: Use bit precise mapping for hole value wires and a more robust hole ↵Alberto Gonzalez2020-06-211-80/+113
| | | | spec for writing to and specializing from a solution file.
* Merge pull request #2173 from whitequark/use-cxx11-final-overridewhitequark2020-06-1915-30/+30
|\ | | | | Use C++11 final/override/[[noreturn]]
| * Use C++11 final/override keywords.whitequark2020-06-1815-30/+30
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