iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Use HTTPS for website links, gatecat email	Claire Xenia Wolf	2021-06-09	1	-1/+1
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-2/+2
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-4/+4
*	Further clean up `passes/sat/eval.cc`.	Alberto Gonzalez	2020-03-30	1	-16/+15
*	Clean up pseudo-private member usage in `passes/sat/eval.cc`.	Alberto Gonzalez	2020-03-28	1	-35/+34
*	Use State::S{0,1}	Eddie Hung	2019-08-06	1	-2/+2
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-3/+3
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-4/+4
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-10/+10
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-1/+1
*	Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-2/+2
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-3/+3
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-6/+6
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-11/+11
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-3/+0
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-6/+2
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+6
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-33/+33
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-33/+33
*	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	1	-4/+4
*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02	1	-1/+1
*	Fixed compiler warining in passes/sat/eval.cc	Clifford Wolf	2013-12-07	1	-2/+2
*	Added eval -set-undef and eval -table	Clifford Wolf	2013-12-07	1	-11/+140
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25	1	-14/+39
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25	1	-4/+20
*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25	1	-9/+30
*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09	1	-17/+13
*	Added verification of SAT model to "eval -vloghammer_report" command	Clifford Wolf	2013-11-09	1	-0/+43
*	Added handling of unconnected/unspecified signals to eval -vloghammer_report	Clifford Wolf	2013-11-06	1	-2/+6
*	Added correct RTL undef handling to eval vloghammer mode	Clifford Wolf	2013-11-06	1	-3/+17
*	Added eval -vloghammer_report mode	Clifford Wolf	2013-11-06	1	-4/+142
*	Added eval -brute_force_equiv_checker_x mode	Clifford Wolf	2013-08-15	1	-5/+15
*	Added "eval" pass	Clifford Wolf	2013-06-19	1	-0/+216