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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 08:40:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:49:43 +0200 |
| commit | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (patch) | |
| tree | ed08831d07df4e799d881349c36acf76bf277791 /passes/sat/eval.cc | |
| parent | 260c19ec5a3adb292158658dd69a352b9325ab64 (diff) | |
| download | yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.tar.gz yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.tar.bz2 yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.zip | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Diffstat (limited to 'passes/sat/eval.cc')
| -rw-r--r-- | passes/sat/eval.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 73235e930..91b428126 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -260,8 +260,8 @@ struct VlogHammerReporter for (int i = 0; i < int(inputs.size()); i++) { RTLIL::Wire *wire = module->wires.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { - ce.set(RTLIL::SigSpec(wire, 1, j), bits.back()); - recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j)); + ce.set(RTLIL::SigSpec::grml(wire, j), bits.back()); + recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j)); recorded_set_vals.bits.push_back(bits.back()); bits.pop_back(); } |