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* sim: For yw cosim, drive parent module's signals for input portsJannis Harder2023-02-131-1/+25
* formalff: Fix crash with _NOT_ gates in -hierarchy modeJannis Harder2023-01-251-1/+1
* sim/formalff: Clock handling for yw cosimJannis Harder2023-01-112-21/+246
* sim: Improvements and fixes for yw cosimJannis Harder2023-01-111-4/+91
* sim: New -append option for Yosys witness cosimJannis Harder2023-01-111-5/+14
* sim: Add Yosys witness (.yw) cosimulationJannis Harder2023-01-111-3/+194
* sim: Only check formal cells during gclk simulation updatesJannis Harder2023-01-111-16/+19
* sim: Internal API to set $initstateJannis Harder2023-01-111-0/+11
* sim: Emit used memory addresses as signals to output tracesJannis Harder2023-01-111-17/+122
* Merge branch 'master' into claire/eqystuffClaire Xen2023-01-112-28/+28
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| * Merge pull request #3537 from jix/xpropJannis Harder2023-01-113-13/+30
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| * | Deprecate gcc-4.8Miodrag Milanovic2023-01-112-28/+28
* | | Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2023-01-113-3/+10
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| * | qbfsat support for cvc5, fixes #3608Miodrag Milanovic2023-01-092-3/+7
| * | formalff: Proper error messages on async inputs for the -clk2ff modeJannis Harder2022-12-091-0/+3
* | | Allow non-unique modules without state in sim writeback-modeClaire Xenia Wolf2022-12-211-4/+5
* | | Add gold-x handing to miter cross port handlingClaire Xenia Wolf2022-12-081-1/+9
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* | miter: Add -make_cover option to cover each output pair differenceJannis Harder2022-11-301-0/+14
* | formalff: Fix -ff2anyinit assertion error for fine FFsJannis Harder2022-11-301-0/+2
* | sim: Improved global clock handlingJannis Harder2022-11-301-13/+14
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* sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-281-6/+22
* Rst docs conversion (#3496)KrystalDelusion2022-11-151-1/+1
* sim: Run a comb-only update step to set past values during FST cosimJannis Harder2022-11-071-12/+11
* Add extra time at the end of a sat VCD traceClaire Xenia Wolf2022-11-011-0/+1
* Add miter -cross optionClaire Xenia Wolf2022-10-241-4/+32
* clk2fflogic: Always correctly handle simultaneously changing signalsJannis Harder2022-10-071-103/+87
* mutate: warn if less mutations possible than number requestedN. Engelhardt2022-10-051-0/+2
* Fitting help messages to 80 character widthKrystalDelusion2022-08-242-24/+28
* sim: -hdlname option to preserve flattened hierarchy in sim outputJannis Harder2022-08-161-9/+41
* clk2fflogic: Generate less unused logic when using verificJannis Harder2022-08-161-1/+4
* formalff: New -setundef optionJannis Harder2022-08-161-0/+335
* formalff: Set new replaced_by_gclk attribute on removed dff's clksJannis Harder2022-08-161-0/+22
* Add the $anyinit cell and the formalff passJannis Harder2022-08-163-1/+194
* support file locations containing spacesMiodrag Milanovic2022-08-081-1/+1
* sim: Fix $anyseq in nested modulesJannis Harder2022-07-221-11/+21
* async2sync: turn FFs with const clks into gclk FFs with feedbackJannis Harder2022-06-301-0/+3
* fmcombine: Add _gold/_gate suffix to memidsJannis Harder2022-06-031-0/+3
* Observe $TMPDIR variable when creating tmp filesMohamed A. Bamakhrama2022-05-271-1/+1
* fix crash when no fst inputMiodrag Milanovic2022-05-041-1/+2
* Start restoring memory state from VCD/FSTMiodrag Milanovic2022-05-041-2/+17
* AIM file could have gaps in or between inputs and initsMiodrag Milanovic2022-05-021-3/+6
* Match $anyseq input if connected to public wireMiodrag Milanovic2022-04-221-6/+12
* Treat $anyseq as input from FSTMiodrag Milanovic2022-04-221-0/+21
* Last sample from input does not represent changeMiodrag Milanovic2022-04-221-1/+2
* latches are always set to zeroMiodrag Milanovic2022-04-221-6/+1
* If not multiclock, output only on clock edgesMiodrag Milanovic2022-04-221-0/+18
* Set init state for all wires from FST and set pastMiodrag Milanovic2022-04-221-13/+12
* Fix multiclock for btor2 witnessMiodrag Milanovic2022-04-221-5/+9
* Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
* Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
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