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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 16:23:39 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 16:23:39 +0200 |
| commit | 4d80bc24c714f700519a2191a8929fe2136e45a3 (patch) | |
| tree | fc8ce8188f418227d634d5b1fcc7c2c854dd3d29 /passes/sat | |
| parent | 9c7deabf9476939e0766fe6bd69b9a7adfeeb48b (diff) | |
| download | yosys-4d80bc24c714f700519a2191a8929fe2136e45a3.tar.gz yosys-4d80bc24c714f700519a2191a8929fe2136e45a3.tar.bz2 yosys-4d80bc24c714f700519a2191a8929fe2136e45a3.zip | |
Treat $anyseq as input from FST
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 345ca3494..5a36f87ec 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -804,6 +804,25 @@ struct SimInstance return did_something; } + void addAdditionalInputs(std::map<Wire*,fstHandle> &inputs) + { + for (auto cell : module->cells()) + { + if (cell->type.in(ID($anyseq))) { + SigSpec sig_y= cell->getPort(ID::Y); + if (sig_y.is_wire()) { + Wire *wire = sig_y.as_wire(); + fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + if (id==0) + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + inputs[wire] = id; + } + } + } + for (auto child : children) + child.second->addAdditionalInputs(inputs); + } + void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values) { for(auto bit : bits) { @@ -1065,6 +1084,8 @@ struct SimWorker : SimShared } } + top->addAdditionalInputs(inputs); + uint64_t startCount = 0; uint64_t stopCount = 0; if (start_time==0) { |