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* Improve proc full_case detection and handling, fixes #931Clifford Wolf2019-04-182-5/+63
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Revert #895Eddie Hung2019-04-161-28/+0
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* Revert "Recognise default entry in case even if all cases covered (fix for ↵Eddie Hung2019-04-151-1/+1
| | | | #931)"
* Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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* proc_mux: Fix crash when trying to optimize non-existant mux to shiftxSylvain Munaut2019-04-031-1/+1
| | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Create one $shiftx per bit in widthEddie Hung2019-03-251-10/+17
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* Add a pmux-to-shiftx optimisation to proc_muxEddie Hung2019-03-231-0/+21
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* proc_clean: fix critical typo.whitequark2019-01-231-1/+1
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* proc_clean: fix fully def check to consider compare/signal length.whitequark2019-01-181-1/+7
| | | | Fixes #790.
* proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-6/+28
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* proc_clean: remove any empty cases at the end of the switch.whitequark2018-12-221-7/+3
| | | | Previously, only completely empty switches were removed.
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-208-16/+16
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Add warnings for driver-driver conflicts between FFs (and other cells) and ↵Clifford Wolf2017-12-121-2/+3
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* Add src attribute to extra cells generated by proc_dlatchClifford Wolf2017-09-091-7/+9
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-7/+19
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* Added "proc_mux -ifx"Clifford Wolf2016-06-062-19/+43
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* Fix all undef-muxes in dlatch input coneClifford Wolf2016-06-021-34/+72
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* Avoid creating undef-muxes when inferring latches in proc_dlatchClifford Wolf2016-06-011-0/+44
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* Fixed proc_mux performance bugClifford Wolf2016-04-251-0/+3
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* Fixed performance bug in proc_dlatchClifford Wolf2016-04-241-2/+61
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* More flexible handling of initialization valuesClifford Wolf2016-04-221-7/+22
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* Added "yosys -D" featureClifford Wolf2016-04-218-8/+8
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* Preserve empty $pmux default casesClifford Wolf2016-03-311-2/+2
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* Improved proc_mux performance for huge always blocksClifford Wolf2015-12-021-36/+153
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* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-028-23/+23
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* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-0/+5
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* Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.Clifford Wolf2015-02-241-2/+4
| | | | (original patch by Andrew Becker <andrew.becker@epfl.ch>)
* Added "proc_dlatch"Clifford Wolf2015-02-123-1/+311
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* Removed SigSpec::extend_xx() apiClifford Wolf2015-01-011-1/+1
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
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* Added log_warning() APIClifford Wolf2014-11-091-2/+2
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-102-2/+2
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* namespace YosysClifford Wolf2014-09-277-22/+58
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* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-122-2/+3
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-1/+1
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-313-81/+81
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-312-5/+5
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* Using log_assert() instead of assert()Clifford Wolf2014-07-284-11/+8
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* Using new obj iterator API in a few placesClifford Wolf2014-07-276-39/+44
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-276-6/+6
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-12/+3
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* Manual fixes for new cell connections APIClifford Wolf2014-07-262-6/+13
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-263-82/+82
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-263-82/+82
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-252-66/+16
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-242-11/+10
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-232-6/+0
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