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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 12:34:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 12:34:51 -0700 |
| commit | adc6efb58468a7e2f85f756d4a9d4686ad0a8c45 (patch) | |
| tree | ab8ad4d7cee30b3f392acf53d90dbf8c1ce30716 /passes/proc | |
| parent | 0deaccbaae436bc94ad5b2913fa39a9368c09ace (diff) | |
| download | yosys-adc6efb58468a7e2f85f756d4a9d4686ad0a8c45.tar.gz yosys-adc6efb58468a7e2f85f756d4a9d4686ad0a8c45.tar.bz2 yosys-adc6efb58468a7e2f85f756d4a9d4686ad0a8c45.zip | |
Recognise default entry in case even if all cases covered (#931)
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 7c334e661..d2f8d9ead 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); + bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; |