iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Fine tune xilinx_dsp pattern matcher	Eddie Hung	2019-08-30	1	-14/+18
*	Remove debug	Eddie Hung	2019-08-30	1	-1/+0
*	Add support for ffM	Eddie Hung	2019-08-30	1	-3/+36
*	New pmgen requires explicit accept	Eddie Hung	2019-08-30	1	-0/+2
*	xilinx_dsp to be sensitive to keep attribute	Eddie Hung	2019-08-15	1	-1/+14
*	Perform C -> PCIN optimisation after pattern matcher	Eddie Hung	2019-08-13	1	-9/+15
*	Check nusers of DSP output, not whole flop	Eddie Hung	2019-08-09	1	-1/+1
*	Cleanup	Eddie Hung	2019-08-09	1	-10/+10
*	Pack partial-product adder DSP48E1 packing	Eddie Hung	2019-08-09	1	-5/+62
*	Remove muxY and ffY for now	Eddie Hung	2019-08-08	1	-30/+28
*	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	Eddie Hung	2019-08-08	1	-1/+1
*	Only pack registers if {A,B,P}REG = 0, do not pack $dffe	Eddie Hung	2019-08-08	1	-3/+6
*	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	Eddie Hung	2019-07-19	1	-10/+10
*	Check if RHS is empty first	Eddie Hung	2019-07-18	1	-0/+2
*	Improve pattern matcher to match subsets of $dffe? cells	Eddie Hung	2019-07-18	1	-10/+14
*	Improve A/B reg packing	Eddie Hung	2019-07-18	1	-6/+8
*	Fix xilinx_dsp index cast	Eddie Hung	2019-07-18	1	-2/+2
*	Pattern matcher to check pool of bits, not exactly	Eddie Hung	2019-07-17	1	-2/+2
*	Signed extension	Eddie Hung	2019-07-16	1	-4/+4
*	Add support {A,B,P}REG packing	Eddie Hung	2019-07-16	1	-29/+52
*	Add xilinx_dsp for register packing	Eddie Hung	2019-07-15	1	-0/+71