| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix memory corruption bug in opt_rmdff | Clifford Wolf | 2017-10-26 | 1 | -0/+3 |
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| * | Fix typo in opt_clean log message | Clifford Wolf | 2017-10-26 | 1 | -1/+1 |
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| * | Revert 90be0d8 as it causes endless loops for some designs | Clifford Wolf | 2017-10-14 | 1 | -1/+0 |
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| * | Fix input vector for reduce cells. | Kaj Tuomi | 2017-10-12 | 1 | -0/+1 |
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| * | Minor changes to opt_demorgan requested during code review | Andrew Zonenberg | 2017-09-14 | 2 | -18/+18 |
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| * | Initial version of opt_demorgan is functioning for AND/OR gates. Not the ↵ | Andrew Zonenberg | 2017-09-12 | 2 | -0/+203 |
| | | | | | prettiest results for bus inputs, but this can be improved | ||||
| * | Don't track , ... contradictions through x/z-bits | Clifford Wolf | 2017-08-25 | 1 | -1/+4 |
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| * | Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr | Clifford Wolf | 2017-08-25 | 1 | -0/+72 |
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| * | Mostly coding style related fixes in rmports pass | Clifford Wolf | 2017-08-15 | 1 | -30/+33 |
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| * | rmports: Now remove ports from cell instances if we optimized them out of ↵ | Andrew Zonenberg | 2017-08-14 | 1 | -2/+35 |
| | | | | | that cell | ||||
| * | ProcessModule is no longer virtual (why was it in the first place?) | Andrew Zonenberg | 2017-08-14 | 1 | -1/+1 |
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| * | rmports now works on all modules in the design, not just the top. | Andrew Zonenberg | 2017-08-14 | 1 | -4/+7 |
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| * | Updated Makefile to reflect opt_rmports being renamed to rmports | Andrew Zonenberg | 2017-08-14 | 1 | -1/+1 |
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| * | Renamed opt_rmports pass to rmports | Andrew Zonenberg | 2017-08-14 | 1 | -5/+5 |
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| * | Improved handling of constant connections in opt_rmports | Andrew Zonenberg | 2017-08-14 | 1 | -0/+2 |
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| * | Fixed handling of cell ports that aren't wires | Andrew Zonenberg | 2017-08-14 | 1 | -0/+3 |
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| * | opt_rmports: Fixed incorrect handling of multi-bit nets | Andrew Zonenberg | 2017-08-14 | 1 | -12/+27 |
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| * | Removed commented out debug code | Andrew Zonenberg | 2017-08-14 | 1 | -4/+0 |
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| * | Added opt_rmports pass (remove unconnected ports from top-level modules) | Andrew Zonenberg | 2017-08-14 | 2 | -0/+133 |
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| * | Add support for set-reset cell variants to opt_rmdff | Clifford Wolf | 2017-08-09 | 1 | -0/+182 |
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| * | Add handling of constant reset signals to opt_rmdff | Clifford Wolf | 2017-08-06 | 1 | -1/+23 |
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| * | Add consolidation of init attributes to opt_clean, some opt_clean log fixes | Clifford Wolf | 2017-07-29 | 1 | -6/+82 |
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| * | Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ↵ | Clifford Wolf | 2017-07-26 | 1 | -0/+47 |
| | | | | | operators | ||||
| * | Excluded $_TBUF_ from opt_merge pass | Salvador E. Tropea | 2017-07-03 | 1 | -0/+1 |
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| * | Fix and_or_buffer optimization in opt_expr for signed operators | Clifford Wolf | 2017-07-01 | 1 | -2/+2 |
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| * | Add $tribuf to opt_merge blacklist | Clifford Wolf | 2017-06-30 | 1 | -0/+1 |
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| * | Squelch trailing whitespace | Larry Doolittle | 2017-04-12 | 1 | -3/+3 |
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| * | Disable opt_merge for $anyseq and $anyconst | Clifford Wolf | 2017-02-28 | 1 | -0/+3 |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+1 |
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| * | Fixed some "used uninitialized" warnings in opt_expr | Clifford Wolf | 2017-02-11 | 1 | -1/+2 |
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| * | Add optimization of (a && 1'b1) and (a || 1'b0) | Clifford Wolf | 2017-02-11 | 1 | -7/+22 |
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| * | Fix issue #306, "Bug in opt -full" | C-Elegans | 2017-02-10 | 1 | -1/+19 |
| | | | | | | | Add check for whether the high bit in the constant expression is greater than the width of the variable, and optimizes that to a constant 1 or 0 | ||||
| * | Fix handling of init attributes with strange width | Clifford Wolf | 2017-02-09 | 2 | -3/+9 |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -1/+1 |
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| * | Fix indenting and log messages in code merged from opt_compare_pr | Clifford Wolf | 2017-01-31 | 1 | -102/+120 |
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| * | Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into ↵ | Clifford Wolf | 2017-01-31 | 1 | -1/+103 |
| |\ | | | | | | | C-Elegans-opt_compare_pr | ||||
| | * | Refactor and generalize the comparision optimization | C-Elegans | 2017-01-30 | 1 | -22/+42 |
| | | | | | | | | | | | | | | | | | Generalizes the optimization to: a < C, a >= C, C > a, C <= a | ||||
| | * | Do not use b.as_int() in calculation of bit set | C-Elegans | 2017-01-21 | 1 | -8/+29 |
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| | * | Optimize compares to powers of 2 | C-Elegans | 2017-01-16 | 4 | -81/+61 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove opt_compare and put comparison pass in opt_expr assuming a [7:0] is unsigned a >= (1<<x) becomes |a[7:x] a < (1<<x) becomes !a[7:x] Additionally: a >= 0 becomes constant true, a < 0 becomes constant false delete opt_compare.cc revert opt.cc to commit b7cfb7dbd (remove opt_compare step) | ||||
| | * | Fix issue #269, optimize signed compare with 0 | C-Elegans | 2017-01-15 | 3 | -0/+81 |
| | | | | | | | | | | | | | | | | | add opt_compare pass and add it to opt for a < 0: if a is signed, replace with a[max_bit-1] for a >= 0: if a is signed, replace with ~a[max_bit-1] | ||||
| * | | Improve opt_rmdff support for $dlatch cells | Clifford Wolf | 2017-01-31 | 1 | -4/+22 |
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| * | Added opt_rmdff support for $ff cells | Clifford Wolf | 2016-10-14 | 1 | -5/+13 |
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| * | Added "opt_rmdff -keepdc" | Clifford Wolf | 2016-09-30 | 2 | -7/+20 |
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| * | Improved init spec handling in opt_rmdff, modernized the code a bit | Clifford Wolf | 2016-08-30 | 1 | -39/+82 |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+1 |
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| * | Added "wreduce -memx" | Clifford Wolf | 2016-08-20 | 1 | -3/+14 |
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| * | Optimize memory address port width in wreduce and memory_collect, not ↵ | Clifford Wolf | 2016-08-19 | 1 | -0/+18 |
| | | | | | verilog front-end | ||||
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+1 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -1/+1 |
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| * | Added opt_expr support for div/mod by power-of-two | Clifford Wolf | 2016-05-29 | 1 | -0/+69 |
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index : iCE40/yosys | |
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