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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-04-08 20:54:31 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-12 15:11:09 +0200 |
| commit | 2021ddecb39d3848e180cd7e078facf82132440f (patch) | |
| tree | a768dd33906dae73482f79cd78c8bce8ddd56f0d /passes/opt | |
| parent | 41d4e91f388f41c97f71567cd5a0f5652a5968fd (diff) | |
| download | yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.gz yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.bz2 yosys-2021ddecb39d3848e180cd7e078facf82132440f.zip | |
Squelch trailing whitespace
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 236908060..07cdf4652 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1217,7 +1217,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons //references the constant signal in the comparison RTLIL::SigSpec sigConst; - // note that this signal must be constant for the optimization + // note that this signal must be constant for the optimization // to take place, but it is not checked beforehand. // If new passes are added, this signal must be checked for const-ness @@ -1307,10 +1307,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec a_prime(RTLIL::State::S0, 1); if(is_lt){ a_prime[0] = RTLIL::State::S1; - log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1); + log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1); } else{ - log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1); + log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1); } module->connect(cell->getPort("\\Y"), a_prime); module->remove(cell); |