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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 11:18:09 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 11:18:09 -0700 |
| commit | 0ee27d0226dcafad798eefdd26480dde1c186e98 (patch) | |
| tree | 47df21013d6500170d1df17336e8a0b50ecdee93 /passes/opt | |
| parent | bd2ac68769ebddf8c239eeaf26d43d30453db583 (diff) | |
| download | yosys-0ee27d0226dcafad798eefdd26480dde1c186e98.tar.gz yosys-0ee27d0226dcafad798eefdd26480dde1c186e98.tar.bz2 yosys-0ee27d0226dcafad798eefdd26480dde1c186e98.zip | |
ProcessModule is no longer virtual (why was it in the first place?)
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/rmports.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index f08d7b126..39cef12e6 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -48,7 +48,7 @@ struct RmportsPassPass : public Pass { ProcessModule(mod); } - virtual void ProcessModule(RTLIL::Module* module) + void ProcessModule(RTLIL::Module* module) { log("Finding unconnected ports in module %s\n", module->name.c_str()); |