iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	2	-5/+5
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	2	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-4/+4
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-1/+1
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-1/+1
*	Fixed manual/CHAPTER_Prog/stubnets.cc	Clifford Wolf	2014-07-23	1	-2/+2
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-12/+7
*	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	Clifford Wolf	2014-07-16	1	-3/+4
*	small changes in presentation	Clifford Wolf	2014-07-02	1	-5/+2
*	Tiny fix in presentation	Clifford Wolf	2014-06-29	1	-1/+1
*	Progress in presentation	Clifford Wolf	2014-06-29	2	-0/+97
*	Progress in presentation	Clifford Wolf	2014-06-26	7	-79/+105
*	Progress in presentation	Clifford Wolf	2014-06-22	7	-42/+503
*	fixed typo	Clifford Wolf	2014-06-21	1	-1/+1
*	Progress in presentation	Clifford Wolf	2014-06-21	9	-23/+188
*	Progress in presentation	Clifford Wolf	2014-06-14	5	-3/+109
*	Progress in presentation	Clifford Wolf	2014-05-06	1	-8/+63
*	Typos and grammar fixes through chapter 4.	Anthony J. Bentley	2014-05-02	2	-32/+32
*	Typos and grammar fixes through chapter 2.	Anthony J. Bentley	2014-04-11	3	-21/+21
*	POSIX find requires a path argument.	Anthony J. Bentley	2014-04-04	1	-1/+1
*	Progress in presentation	Clifford Wolf	2014-02-21	6	-32/+113
*	Progress in presentation	Clifford Wolf	2014-02-21	5	-19/+177
*	Progress in presentation	Clifford Wolf	2014-02-20	4	-11/+51
*	Progress in presentation	Clifford Wolf	2014-02-20	5	-0/+207
*	Progress in presentation	Clifford Wolf	2014-02-20	10	-10/+152
*	Progress in presentation	Clifford Wolf	2014-02-18	6	-3/+72
*	Progress in presentation	Clifford Wolf	2014-02-17	3	-9/+37
*	Progress in presentation	Clifford Wolf	2014-02-16	5	-1/+80
*	Progress in presentation	Clifford Wolf	2014-02-16	5	-1/+79
*	Progress in presentation	Clifford Wolf	2014-02-16	6	-3/+74
*	Progress in presentation	Clifford Wolf	2014-02-16	6	-1/+114
*	Improved "make manual" and "make clean"	Clifford Wolf	2014-02-11	3	-3/+5
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+4
*	presentation progress	Clifford Wolf	2014-02-06	10	-12/+265
*	presentation progress	Clifford Wolf	2014-02-05	4	-64/+221
*	presentation progress	Clifford Wolf	2014-02-05	5	-3/+62
*	presentation progress	Clifford Wolf	2014-02-05	5	-8/+230
*	presentation progress	Clifford Wolf	2014-02-04	3	-34/+104
*	presentation progress	Clifford Wolf	2014-02-04	9	-3/+206
*	presentation progress	Clifford Wolf	2014-02-04	2	-11/+55
*	presentation progress	Clifford Wolf	2014-02-03	6	-1/+152
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+7
*	presentation progress	Clifford Wolf	2014-02-02	19	-40/+194
*	presentation progress	Clifford Wolf	2014-02-02	10	-0/+80
*	presentation progress	Clifford Wolf	2014-02-02	2	-10/+20
*	presentation progress	Clifford Wolf	2014-02-02	1	-10/+158
*	Progress on presentation	Clifford Wolf	2014-01-31	3	-5/+194
*	presentation progress	Clifford Wolf	2014-01-30	2	-7/+157
*	presentation progress	Clifford Wolf	2014-01-29	2	-4/+36
*	presentation progress	Clifford Wolf	2014-01-29	10	-2/+174