Refactoring: Renamed RTLIL::Module::wires to wires_

2 files changed, 4 insertions, 4 deletions

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index f67ffe1e8..9eacfbcb5 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -43,7 +43,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 	}
 
 	// for each wire in the module
-	for (auto &wire_iter : module->wires)
+	for (auto &wire_iter : module->wires_)
 	{
 		RTLIL::Wire *wire = wire_iter.second;
 
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index cf8a4add8..0cd1da808 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -14,7 +14,7 @@ struct MyPass : public Pass {
         log("Modules in current design:\n");
         for (auto &mod : design->modules)
             log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
-                    mod.second->wires.size(), mod.second->cells.size());
+                    mod.second->wires_.size(), mod.second->cells.size());
     }
 } MyPass;
 
@@ -58,8 +58,8 @@ struct Test2Pass : public Pass {
 
         RTLIL::Module *module = design->modules.at("\\test");
 
-        RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
-                                                   y(module->wires.at("\\y"));
+        RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
+                                                   y(module->wires_.at("\\y"));
         log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
 
         SigMap sigmap(module);