| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | manual: explain RTLIL::Wire::{upto,offset}. | whitequark | 2020-02-09 | 1 | -0/+7 |
| * | manual: explain the purpose of `sync always`. | whitequark | 2019-07-02 | 1 | -2/+3 |
| * | Explain exact semantics of switch and case rules in the manual. | whitequark | 2019-06-19 | 1 | -0/+12 |
| * | manual: document $meminit cell and memory_* passes. | whitequark | 2018-12-20 | 1 | -2/+2 |
| * | Renamed opt_share to opt_merge | Clifford Wolf | 2016-03-31 | 1 | -2/+2 |
| * | Renamed opt_const to opt_expr | Clifford Wolf | 2016-03-31 | 1 | -1/+1 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -2/+2 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 |
| * | Typos and grammar fixes through chapter 4. | Anthony J. Bentley | 2014-05-02 | 1 | -25/+25 |
| * | presentation progress | Clifford Wolf | 2014-02-03 | 1 | -1/+0 |
| * | Updated manual | Clifford Wolf | 2013-09-15 | 1 | -2/+4 |
| * | Added RTLIL and Liberty syntax highlighting to manual | Clifford Wolf | 2013-07-25 | 1 | -3/+3 |
| * | Added Yosys Manual | Clifford Wolf | 2013-07-20 | 1 | -0/+525 |
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index : iCE40/yosys | |
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