iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	43	-27/+258
*	Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff	Eddie Hung	2020-05-18	34	-1853/+1656
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\| *	abc9: use (* abc9_keep ) instead of ( abc9_scc *); apply to $_DFF_?_	Eddie Hung	2020-05-14	5	-23/+11
\| *	abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)	Eddie Hung	2020-05-14	1	-4/+6
\| *	abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it	Eddie Hung	2020-05-14	4	-25/+13
\| *	Fix broken test when ignoring abc9_flop with init == 1'b1	Eddie Hung	2020-05-14	1	-3/+0
\| *	abc9_ops/xaiger: further reducing Module::derive() calls by ...	Eddie Hung	2020-05-14	4	-135/+121
\| *	Cleanup; reduce Module::derive() calls	Eddie Hung	2020-05-14	4	-153/+164
\| *	ecp5: latches_map.v if not -asyncprld	Eddie Hung	2020-05-14	1	-2/+2
\| *	ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v	Eddie Hung	2020-05-14	4	-43/+3
\| *	ecp5: fix rebase mistake	Eddie Hung	2020-05-14	1	-3/+3
\| *	abc9: update to =_$abc9_flops pattern which includes whiteboxes	Eddie Hung	2020-05-14	1	-3/+3
\| *	abc9_ops: update docs	Eddie Hung	2020-05-14	1	-11/+10
\| *	xilinx: gate specify/attributes from iverilog	Eddie Hung	2020-05-14	1	-1/+3
\| *	abc9: only do +/abc9_map if `DFF	Eddie Hung	2020-05-14	2	-1/+6
\| *	abc9: rework submod -- since it won't move (* keep *) cells	Eddie Hung	2020-05-14	2	-34/+29
\| *	ecp5: TRELLIS_FF bypass path only in async mode	Eddie Hung	2020-05-14	1	-8/+8
\| *	timinginfo: ignore $specify2 cells if EN is false	Eddie Hung	2020-05-14	1	-0/+3
\| *	xilinx/ice40/ecp5: zinit requires selected wires, so select them all	Eddie Hung	2020-05-14	3	-4/+4
\| *	abc9_ops: move assert	Eddie Hung	2020-05-14	1	-1/+1
\| *	abc9: put 'aigmap' back	Eddie Hung	2020-05-14	1	-0/+1
\| *	xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells	Eddie Hung	2020-05-14	3	-4/+198
\| *	abc9_ops: fix bypass boxes using (* abc9_bypass *)	Eddie Hung	2020-05-14	2	-14/+10
\| *	abc9_ops: tidy up, suppress error if no boxes/holes	Eddie Hung	2020-05-14	1	-18/+18
\| *	abc9_ops: -prep_delays to not insert delay box if input connection is const	Eddie Hung	2020-05-14	1	-0/+2
\| *	abc9_ops: cleanup; -prep_dff -> -prep_dff_submod	Eddie Hung	2020-05-14	2	-22/+14
\| *	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	Eddie Hung	2020-05-14	11	-941/+667
\| *	abc9_ops: -reintegrate to handle $_FF_; cleanup	Eddie Hung	2020-05-14	1	-22/+18
\| *	xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity	Eddie Hung	2020-05-14	1	-16/+5
\| *	aiger: -xaiger to return $_FF_ flops	Eddie Hung	2020-05-14	1	-15/+2
\| *	abc9: not enough to techmap_fail on (* init=1 *), hide them using $__	Eddie Hung	2020-05-14	4	-12/+48
\| *	abc9: test to use box file instead of auto	Eddie Hung	2020-05-14	3	-2/+5
\| *	abc9: restore selected_modules()	Eddie Hung	2020-05-14	1	-1/+1
\| *	synth_*: no need to explicitly read +/abc9_model.v	Eddie Hung	2020-05-14	4	-4/+3
\| *	Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"	Eddie Hung	2020-05-14	1	-4/+0
\| *	abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too	Eddie Hung	2020-05-14	7	-24/+88
\| *	kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero	Eddie Hung	2020-05-14	1	-10/+6
\| *	abc9_ops: -prep_dff_map to error if async flop found	Eddie Hung	2020-05-14	2	-9/+7
\| *	Uncomment negative setup times; clamp to zero for connectivity	Eddie Hung	2020-05-14	1	-13/+29
\| *	abc9: remove redundant wbflip	Eddie Hung	2020-05-14	1	-1/+0
\| *	xaiger: always sort input/output bits by port id	Eddie Hung	2020-05-14	1	-12/+10
\| *	abc9: generate $abc9_holes design instead of <name>$holes	Eddie Hung	2020-05-14	3	-18/+28
\| *	abc9_ops: more robust	Eddie Hung	2020-05-14	1	-8/+14
\| *	abc9: suppress warnings when no compatible + used flop boxes formed	Eddie Hung	2020-05-14	3	-38/+66
\| *	xilinx: update abc9_dff tests	Eddie Hung	2020-05-14	1	-18/+45
\| *	xilinx: remove no-longer-relevant test	Eddie Hung	2020-05-14	1	-91/+0
\| *	aiger/xaiger: use odd for negedge clk, even for posedge	Eddie Hung	2020-05-14	2	-10/+13
\| *	abc9: cleanup	Eddie Hung	2020-05-14	1	-7/+11
\| *	Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"	Eddie Hung	2020-05-14	3	-220/+64
\| *	abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output	Eddie Hung	2020-05-14	1	-1/+5