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* satgen import sigbit apiClifford Wolf2014-10-031-1/+17
* added resource sharing of $macc cellsClifford Wolf2014-10-031-0/+9
* Added $_BUF_ cell typeClifford Wolf2014-10-032-0/+4
* Added support for "keep" on modulesClifford Wolf2014-09-291-0/+5
* namespace YosysClifford Wolf2014-09-276-16/+28
* Assert on new logic loops in "share" passClifford Wolf2014-09-211-1/+1
* Initialize RTLIL::Const from std::vector<bool>Clifford Wolf2014-09-192-1/+9
* Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)Clifford Wolf2014-09-161-0/+2
* Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-151-0/+60
* Fixed monitor notifications for removed cellClifford Wolf2014-09-141-0/+3
* Added "synth" commandClifford Wolf2014-09-141-10/+4
* Simplified $fa undef modelClifford Wolf2014-09-082-14/+5
* Added $lcu cell typeClifford Wolf2014-09-084-0/+84
* Added "$fa" cell typeClifford Wolf2014-09-084-0/+90
* Added $macc eval modelClifford Wolf2014-09-061-0/+22
* Added $macc SAT modelClifford Wolf2014-09-061-0/+71
* Added $macc cell typeClifford Wolf2014-09-063-7/+189
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-3/+3
* Removed $bu0 cell typeClifford Wolf2014-09-045-31/+6
* Using $pos models for $bu0Clifford Wolf2014-09-032-2/+2
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-032-6/+5
* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-022-2/+1
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-022-6/+6
* Added ConstEval model for $alu cellsClifford Wolf2014-09-011-0/+56
* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-012-36/+32
* Fixed return size of const_*() eval functionsClifford Wolf2014-08-311-1/+5
* Added RTLIL::Const::size()Clifford Wolf2014-08-311-0/+2
* Added eval model for $lut cellsClifford Wolf2014-08-311-0/+26
* Typo fixes in cell->*Param() APIClifford Wolf2014-08-311-4/+4
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-312-4/+57
* Added design->scratchpadClifford Wolf2014-08-302-0/+72
* Added $alu cell typeClifford Wolf2014-08-302-0/+16
* Fixed module->addPmux()Clifford Wolf2014-08-301-1/+0
* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-242-6/+9
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-236-189/+19
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-233-13/+19
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-235-49/+36
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-226-10/+40
* Added "plugin" commandClifford Wolf2014-08-223-10/+17
* Added mod->addGate() methods for new gate typesClifford Wolf2014-08-192-63/+100
* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-171-4/+2
* Improved sig.remove2() performanceClifford Wolf2014-08-171-2/+11
* Added stackmap<> containerClifford Wolf2014-08-172-2/+109
* Renamed toposort.h to utils.hClifford Wolf2014-08-171-0/+0
* Added module->uniquify()Clifford Wolf2014-08-162-0/+25
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-164-19/+152
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-161-31/+37
* Added log_spacer()Clifford Wolf2014-08-163-2/+20
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-152-6/+5
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