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* sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-281-0/+1
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-0/+12
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* satgen: Move importCell out of the header.Marcelina Kościelnicka2020-07-191-1165/+1
| | | | | This function has no hope of ever getting inlined anyway, and it speeds up yosys compile time by 7%.
* Add flooring division operatorXiretza2020-05-281-4/+17
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-9/+22
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-56/+56
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* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-118/+118
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* More use of IdString::in()Eddie Hung2019-08-151-26/+25
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* Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-111-261/+261
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* RTLIL::S{0,1} -> State::S{0,1} for headersEddie Hung2019-08-071-1/+1
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-2/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-1/+1
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-1/+18
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* Fix undef propagation bug in $pmux SAT modelClifford Wolf2017-02-051-14/+4
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* Added $anyseq cell typeClifford Wolf2016-10-141-2/+7
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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-1/+1
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* Added SatGen support for $anyconstClifford Wolf2016-07-271-0/+22
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* Removed $predict support from SatGenClifford Wolf2016-07-271-9/+0
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* Added satgen initstate supportClifford Wolf2016-07-221-0/+27
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-3/+3
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
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* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+9
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* Added $sop SAT modelClifford Wolf2016-06-171-0/+82
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
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* Added $assume cell typeClifford Wolf2015-02-261-0/+30
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* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-1/+31
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* Added "equiv_simple -undef"Clifford Wolf2015-01-311-0/+14
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* Various equiv_simple improvementsClifford Wolf2015-01-221-0/+19
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* Fixed a few VS warningsClifford Wolf2014-10-171-1/+1
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* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
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* Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32Clifford Wolf2014-10-101-52/+52
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-32/+32
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* satgen import sigbit apiClifford Wolf2014-10-031-1/+17
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* namespace YosysClifford Wolf2014-09-271-0/+5
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* Simplified $fa undef modelClifford Wolf2014-09-081-14/+1
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* Added $lcu cell typeClifford Wolf2014-09-081-0/+32
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* Added "$fa" cell typeClifford Wolf2014-09-081-0/+49
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* Added $macc SAT modelClifford Wolf2014-09-061-0/+71
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* Removed $bu0 cell typeClifford Wolf2014-09-041-3/+3
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* Using $pos models for $bu0Clifford Wolf2014-09-031-1/+1
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* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-031-4/+3
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* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-021-3/+4
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* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-1/+50
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-161-7/+81
| | | | $_OAI4_
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
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* RIP $safe_pmuxClifford Wolf2014-08-141-9/+1
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-85/+85
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