iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-5/+27
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-6/+0
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22	1	-30/+13
*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22	1	-24/+85
*	Added information on all internal cell types to internal checker	Clifford Wolf	2013-11-11	1	-0/+340
*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09	1	-0/+14
*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07	1	-1/+1
*	Fixed type of sign extension in opt_const $eq/$ne handling	Clifford Wolf	2013-11-07	1	-0/+16
*	Added eval -vloghammer_report mode	Clifford Wolf	2013-11-06	1	-0/+3
*	Changed NEW_WIRE API to return the wire, not the signal	Clifford Wolf	2013-10-18	1	-1/+1
*	Added RTLIL NEW_WIRE macro	Clifford Wolf	2013-10-18	1	-0/+9
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	1	-0/+89
*	Added "eval" pass	Clifford Wolf	2013-06-19	1	-0/+85
*	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	Clifford Wolf	2013-06-18	1	-2/+31
*	Added "dump" command (part ilang backend)	Clifford Wolf	2013-06-02	1	-7/+7
*	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29	1	-3/+10
*	Create nice errors when calling RTLIL::Module::derive() of base class	Clifford Wolf	2013-03-26	1	-3/+3
*	initial import	Clifford Wolf	2013-01-05	1	-0/+1081