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author | Clifford Wolf <clifford@clifford.at> | 2013-10-18 13:25:24 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-10-18 13:25:24 +0200 |
commit | cc5e379eca3cea2369c49ebf8e554b35614495de (patch) | |
tree | 71e6cd45aca3d4e28332ed60b9bf5059f037889e /kernel/rtlil.cc | |
parent | 0836a1f2ba3990fff81b353adfe93cfd35ae7246 (diff) | |
download | yosys-cc5e379eca3cea2369c49ebf8e554b35614495de.tar.gz yosys-cc5e379eca3cea2369c49ebf8e554b35614495de.tar.bz2 yosys-cc5e379eca3cea2369c49ebf8e554b35614495de.zip |
Added RTLIL NEW_WIRE macro
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6271aeef8..5075215cd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -382,6 +382,15 @@ RTLIL::Module *RTLIL::Module::clone() const return new_mod; } +RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name) +{ + RTLIL::Wire *wire = new RTLIL::Wire; + wire->width = width; + wire->name = name; + add(wire); + return wire; +} + void RTLIL::Module::add(RTLIL::Wire *wire) { assert(!wire->name.empty()); |