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* Add proper SVA seq.triggered supportClifford Wolf2018-03-043-37/+102
* Add Verific SVA support for "seq and seq" expressionsClifford Wolf2018-03-041-24/+94
* Refactor Verific SVA importer property parserClifford Wolf2018-03-041-56/+82
* Add VerificClocking class and refactor Verific DFF handlingClifford Wolf2018-03-043-126/+196
* Add SVA support for sequence ORClifford Wolf2018-03-031-22/+33
* Fix handling of SVA "until seq.triggered" propertiesClifford Wolf2018-03-021-7/+25
* Update SVA cheat sheet in verificsva.ccClifford Wolf2018-03-021-2/+4
* Fix in Verific SVA importer handling of until_withClifford Wolf2018-03-011-7/+5
* Fixes and improvements in Verific SVA importerClifford Wolf2018-03-013-83/+136
* Add $rose/$fell support to Verific bindingsClifford Wolf2018-03-011-3/+22
* Add support for PRIM_SVA_UNTIL to new SVA importerClifford Wolf2018-02-281-0/+27
* Add DFSM generator to verific SVA importerClifford Wolf2018-02-281-19/+272
* Continue refactoring of Verific SVA importer codeClifford Wolf2018-02-283-671/+172
* Major redesign of Verific SVA importerClifford Wolf2018-02-271-5/+573
* Add handling of verific OPER_REDUCE_NORClifford Wolf2018-02-261-0/+6
* Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTORClifford Wolf2018-02-261-0/+13
* Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUXClifford Wolf2018-02-261-0/+25
* Add "SVA syntax cheat sheet" comment to verificsva.ccClifford Wolf2018-02-261-0/+34
* Add $allconst and $allseq cell typesClifford Wolf2018-02-233-4/+6
* Add Verific SVA support for ranges in repetition operatorClifford Wolf2018-02-221-5/+26
* Add support for SVA throughout via VerificClifford Wolf2018-02-211-2/+6
* Add support for SVA sequence concatenation ranges via verificClifford Wolf2018-02-181-16/+124
* Add support for SVA until statements via VerificClifford Wolf2018-02-182-34/+119
* Move Verific SVA importer to extra C++ source fileClifford Wolf2018-02-184-1279/+1370
* Merge Verific SVA preprocessor and SVA importerClifford Wolf2018-02-181-79/+44
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2018-02-161-0/+6
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| * Improve handling of "bus" pins in liberty front-end (some files use bus.pin.d...Clifford Wolf2018-02-151-0/+6
* | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFFClifford Wolf2018-02-151-1/+1
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* Fix single-bit $stable handling in verific front-endClifford Wolf2018-02-011-0/+22
* Add Verific attribute handling for assert/assume/cover/live/fair cellsClifford Wolf2018-01-311-10/+16
* Fix permissions on verific vdb filesClifford Wolf2018-01-281-0/+1
* Fixed handling of synchronous and asynchronous assertion/assumption/cover in ...Clifford Wolf2018-01-231-27/+29
* Add support for "yosys -E"Clifford Wolf2018-01-072-2/+5
* Merge pull request #479 from Fatsie/latch_without_dataClifford Wolf2018-01-051-4/+23
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| * Some standard cell libraries include a latch with only set/reset.Staf Verhaegen2018-01-031-4/+23
* | Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-052-2/+2
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* Bugfix in verilog_defaults argument parserClifford Wolf2017-12-241-1/+1
* Add support for Verific PRIM_SVA_NOT propertiesClifford Wolf2017-12-101-10/+25
* Add Verific OPER_SVA_STABLE supportClifford Wolf2017-12-101-2/+32
* Refactoring Verific SVA rewriterClifford Wolf2017-12-101-62/+70
* Fix error handling for nested always/initialClifford Wolf2017-12-022-0/+5
* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-232-13/+18
* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
* Accommodate Windows-style paths during include-file processing.William D. Jones2017-11-141-4/+20
* Remove vhdl2verilogClifford Wolf2017-10-252-184/+0
* Remove all PSL support code from verific.ccClifford Wolf2017-10-201-179/+17
* Add "verific -vlog-libdir"Clifford Wolf2017-10-131-0/+12
* Add "verific -vlog-incdir" and "verific -vlog-define"Clifford Wolf2017-10-131-0/+35
* Update Verific READMEClifford Wolf2017-10-131-0/+7
* Add Verific fairness/liveness supportClifford Wolf2017-10-121-11/+32