| Commit message (Expand) | Author | Age | Files | Lines |
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| * | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
| * | Verific updates | Clifford Wolf | 2018-12-06 | 1 | -53/+0 |
| * | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 |
| * | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 |
| * | Allow square brackets in liberty identifiers | Clifford Wolf | 2018-11-05 | 1 | -1/+2 |
| * | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 |
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 3 | -99/+69 |
| * | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 |
| * | Do not generate "reg assigned in a continuous assignment" warnings for "rand ... | Clifford Wolf | 2018-11-01 | 1 | -2/+15 |
| * | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 |
| * | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 1 | -14/+14 |
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| | * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars... | Udi Finkelstein | 2018-10-25 | 1 | -14/+14 |
| * | | Improve read_verilog range out of bounds warning | Clifford Wolf | 2018-10-20 | 1 | -6/+6 |
| * | | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 3 | -134/+108 |
| * | | Support for SystemVerilog interfaces as a port in the top level module + test... | Ruben Undheim | 2018-10-20 | 1 | -3/+105 |
| * | | Fixed memory leak | Ruben Undheim | 2018-10-20 | 1 | -0/+1 |
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| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 6 | -14/+353 |
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| | * | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 |
| | * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 2 | -8/+35 |
| | * | Fix build error with clang | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
| | * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 4 | -8/+89 |
| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 6 | -14/+243 |
| * | | Merge pull request #664 from tklam/ignore-verilog-protect | Clifford Wolf | 2018-10-18 | 1 | -0/+3 |
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| | * | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 |
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| * | | Minor code cleanups in liberty front-end | Clifford Wolf | 2018-10-17 | 1 | -16/+5 |
| * | | Merge pull request #660 from tklam/parse-liberty-detect-ff-latch | Clifford Wolf | 2018-10-17 | 1 | -0/+17 |
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| | * | | detect ff/latch before processing other nodes | argama | 2018-10-14 | 1 | -0/+17 |
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| * | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 |
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| | * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 |
| | * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 21 | -479/+1448 |
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| | * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 |
| * | | | Improve Verific importer blackbox handling | Clifford Wolf | 2018-10-07 | 1 | -2/+14 |
| * | | | Fix compiler warning in verific.cc | Clifford Wolf | 2018-10-05 | 1 | -0/+2 |
| * | | | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 |
| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 |
| * | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
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| | * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
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| * | | | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 3 | -6/+49 |
| * | | | Added support for ommited "parameter" in Verilog-2001 style parameter decl in... | Clifford Wolf | 2018-09-23 | 1 | -3/+9 |
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| * | | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 3 | -2/+16 |
| * | | Add "make coverage" | Clifford Wolf | 2018-08-27 | 6 | -12/+10 |
| * | | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 |
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| | * | | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| | * | | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout... | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| | * | | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| * | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 3 | -9/+20 |
| * | | | Add "verific -work" help message | Clifford Wolf | 2018-08-22 | 1 | -0/+7 |
| * | | | Add Verific -work parameter | Clifford Wolf | 2018-08-22 | 1 | -8/+18 |
| * | | | Add "verific -set-<severity> <msg_id>.." | Clifford Wolf | 2018-08-16 | 1 | -14/+52 |
| * | | | Verific workaround for VIPER ticket 13851 | Clifford Wolf | 2018-08-16 | 1 | -0/+3 |
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