| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 5 | -11/+42 |
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| | * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 5 | -11/+42 |
| * | | Ignore a/i/o/h XAIGER extensions | Eddie Hung | 2019-04-17 | 1 | -0/+7 |
| * | | Forgot backslashes | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
| * | | Handle __dummy_o__ and __const[01]__ in read_aiger not abc | Eddie Hung | 2019-04-12 | 1 | -0/+4 |
| * | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 1 | -12/+32 |
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| | * | | Fix inout handling for -map option | Eddie Hung | 2019-04-12 | 1 | -10/+30 |
| * | | | Also cope with duplicated CIs | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
| * | | | Cope with an output having same name as an input (i.e. CO) | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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| * | | parse_aiger() to rename all $lut cells after "clean" | Eddie Hung | 2019-04-10 | 1 | -24/+21 |
| * | | Fix spacing | Eddie Hung | 2019-04-08 | 1 | -29/+29 |
| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 15 | -142/+500 |
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| | * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 3 | -3/+14 |
| | * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 |
| | * | Add "read -verific" and "read -noverific" | Clifford Wolf | 2019-03-27 | 1 | -6/+28 |
| | * | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 1 | -15/+71 |
| | * | Fix mem2reg handling of memories with upto data ports, fixes #888 | Clifford Wolf | 2019-03-21 | 1 | -1/+10 |
| | * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 |
| | * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 3 | -15/+42 |
| | * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 8 | -110/+348 |
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| | | * | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 1 | -1/+5 |
| | | * | Improve handling of "full_case" attributes | Clifford Wolf | 2019-03-14 | 1 | -0/+9 |
| | | * | Improve handling of memories used in mem index expressions on LHS of an assig... | Clifford Wolf | 2019-03-12 | 1 | -5/+16 |
| | | * | Remove outdated "blocking assignment to memory" warning | Clifford Wolf | 2019-03-12 | 1 | -10/+0 |
| | | * | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 | Clifford Wolf | 2019-03-12 | 1 | -6/+8 |
| | | * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 2 | -92/+66 |
| | | * | Merge pull request #858 from YosysHQ/clifford/svalabels | Clifford Wolf | 2019-03-09 | 5 | -56/+201 |
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| | | | * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 2 | -44/+113 |
| | | | * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 3 | -26/+89 |
| | | | * | Add hack for handling SVA labels via Verific | Clifford Wolf | 2019-03-07 | 1 | -1/+14 |
| | | * | | Update help message for -chparam | Eddie Hung | 2019-03-09 | 1 | -1/+2 |
| | | * | | Add -chparam option to verific command | Eddie Hung | 2019-03-09 | 1 | -2/+18 |
| | | * | | Fix spelling | Eddie Hung | 2019-03-09 | 1 | -1/+1 |
| | | * | | Fix handling of task output ports in clocked always blocks, fixes #857 | Clifford Wolf | 2019-03-07 | 1 | -15/+18 |
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| | | * | Merge pull request #848 from YosysHQ/clifford/fix763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
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| | | | * | Fix error for wire decl in always block, fixes #763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
| | | * | | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 2 | -0/+20 |
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| | | * | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| | | * | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 |
| | | * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 2 | -0/+13 |
| | | * | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | * | | Add author name | Eddie Hung | 2019-03-19 | 1 | -0/+1 |
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 3 | -12/+23 |
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| | * | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | * | | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | * | | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 2 | -9/+12 |
| | * | | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 |
| | * | | Fix segfault in printing of some internal error messages | Clifford Wolf | 2019-02-21 | 1 | -2/+2 |
| * | | | parse_xaiger() to really pass single and multi-bit inout tests | Eddie Hung | 2019-02-26 | 1 | -10/+12 |
| * | | | parse_xaiger() to cope with multi bit inouts | Eddie Hung | 2019-02-26 | 1 | -0/+11 |
