| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixed handling of positional module parameters | Clifford Wolf | 2013-04-26 | 1 | -6/+4 |
| * | Only use sha1 checksums for names of parametric modules when the verbose form... | Clifford Wolf | 2013-04-26 | 1 | -9/+20 |
| * | Fixed a bug in AST frontend for cases with non-blocking assigned variables as... | Clifford Wolf | 2013-04-13 | 1 | -4/+4 |
| * | Now only use value from "initial" when no matching "always" block is found | Clifford Wolf | 2013-03-31 | 3 | -7/+31 |
| * | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) | Clifford Wolf | 2013-03-31 | 5 | -3/+15 |
| * | Implemented proper handling of stub placeholder modules | Clifford Wolf | 2013-03-28 | 3 | -6/+30 |
| * | Improvements and bugfixes for generate blocks with local signals | Clifford Wolf | 2013-03-26 | 2 | -4/+2 |
| * | Fixed handling of unconditional generate blocks | Clifford Wolf | 2013-03-26 | 2 | -1/+19 |
| * | Added nosync attribute and some async reset related fixes | Clifford Wolf | 2013-03-25 | 3 | -34/+16 |
| * | Added mem2reg option to verilog frontend | Clifford Wolf | 2013-03-24 | 4 | -11/+28 |
| * | Another fix in mem2reg ast simplify logic | Clifford Wolf | 2013-03-24 | 1 | -1/+3 |
| * | Improved mem2reg handling in ast simplifier | Clifford Wolf | 2013-03-24 | 2 | -5/+35 |
| * | Tiny fixes to verilog parser | Clifford Wolf | 2013-03-23 | 2 | -1/+9 |
| * | Added help messages to ilang and verilog frontends | Clifford Wolf | 2013-03-01 | 2 | -2/+57 |
| * | Moved stand-alone libs to libs/ directory and added libs/subcircuit | Clifford Wolf | 2013-02-27 | 4 | -4/+4 |
| * | Added support for verilog genblock[index].member syntax | Clifford Wolf | 2013-02-26 | 4 | -11/+33 |
| * | Added support for "always @(*)" | Clifford Wolf | 2013-01-16 | 1 | -0/+3 |
| * | added .gitignore files | Clifford Wolf | 2013-01-05 | 2 | -0/+8 |
| * | initial import | Clifford Wolf | 2013-01-05 | 17 | -0/+5999 |
