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* Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
* Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-1821-479/+1448
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| * Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
| * Add "make coverage"Clifford Wolf2018-08-276-12/+10
| * Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
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| | * Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | * Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...Udi Finkelstein2018-08-201-10/+22
| | * A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| * | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-233-9/+20
| * | Add "verific -work" help messageClifford Wolf2018-08-221-0/+7
| * | Add Verific -work parameterClifford Wolf2018-08-221-8/+18
| * | Add "verific -set-<severity> <msg_id>.."Clifford Wolf2018-08-161-14/+52
| * | Verific workaround for VIPER ticket 13851Clifford Wolf2018-08-161-0/+3
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| * Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-157-23/+23
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| | * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-207-23/+23
| * | Merge pull request #590 from hzeller/remaining-file-errorClifford Wolf2018-08-151-15/+15
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| | * | Fix remaining log_file_error(); emit dependent file references in new line.Henner Zeller2018-07-201-15/+15
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| * | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-155-4/+57
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| * \ \ Merge pull request #562 from udif/pr_fix_illegal_port_declClifford Wolf2018-08-151-3/+6
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| | * | | Detect illegal port declaration, e.g input/output/inout keyword must be the f...Udi Finkelstein2018-06-061-3/+6
| * | | | Fixed use of char array for string in blifparse error handlingClifford Wolf2018-08-081-5/+5
| * | | | Report error reason on same line as syntax error.litghost2018-08-081-6/+9
| * | | | Use log_warning which does not immediately terminate.litghost2018-08-031-3/+3
| * | | | Add BLIF parsing support for .conn and .cnamelitghost2018-08-021-3/+30
| * | | | Verific: Produce errors for instantiating unknown moduleClifford Wolf2018-07-221-0/+3
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| * | | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-204-137/+131
| * | | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-203-82/+79
| * | | Provide source-location logging.Henner Zeller2018-07-191-3/+2
| * | | Fix handling of eventually properties in verific importerClifford Wolf2018-07-171-2/+4
| * | | Fix verific -vlog-incdir and -vlog-libdir handlingClifford Wolf2018-07-161-2/+13
| * | | Fix "read -incdir"Clifford Wolf2018-07-161-1/+1
| * | | Add "read -incdir"Clifford Wolf2018-07-161-0/+19
| * | | Fix verific eventually handlingClifford Wolf2018-06-291-6/+5
| * | | Add verific support for eventually propertiesClifford Wolf2018-06-291-5/+105
| * | | Add "verific -formal" and "read -formal"Clifford Wolf2018-06-291-7/+15
| * | | Add "read -sv -D" supportClifford Wolf2018-06-281-2/+25
| * | | Add "read -undef"Clifford Wolf2018-06-281-0/+32
| * | | Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
| * | | Add YOSYS_NOVERIFIC env variable for temporarily disabling verificClifford Wolf2018-06-221-22/+40
| * | | Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
| * | | Add automatic verific import in hierarchy commandClifford Wolf2018-06-202-0/+56
| * | | Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
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| * | Add (* gclk *) attribute supportClifford Wolf2018-06-013-0/+20
| * | Add comment to VIPER #13453 work-aroundClifford Wolf2018-05-281-0/+1
| * | Fix Verific handling of single-bit anyseq/anyconst wiresClifford Wolf2018-05-251-2/+4
| * | Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGEClifford Wolf2018-05-241-1/+1
| * | Fix verific handling of anyconst/anyseq attributesClifford Wolf2018-05-242-16/+28
| * | Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
| * | Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
| * | Fix handling of anyconst/anyseq attrs in VHDL code via VerificClifford Wolf2018-05-151-6/+6
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