| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix mem2reg handling of memories with upto data ports, fixes #888 | Clifford Wolf | 2019-03-21 | 1 | -1/+10 |
| * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 |
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 3 | -15/+42 |
| * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 8 | -110/+348 |
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| | * | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 1 | -1/+5 |
| | * | Improve handling of "full_case" attributes | Clifford Wolf | 2019-03-14 | 1 | -0/+9 |
| | * | Improve handling of memories used in mem index expressions on LHS of an assig... | Clifford Wolf | 2019-03-12 | 1 | -5/+16 |
| | * | Remove outdated "blocking assignment to memory" warning | Clifford Wolf | 2019-03-12 | 1 | -10/+0 |
| | * | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 | Clifford Wolf | 2019-03-12 | 1 | -6/+8 |
| | * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 2 | -92/+66 |
| | * | Merge pull request #858 from YosysHQ/clifford/svalabels | Clifford Wolf | 2019-03-09 | 5 | -56/+201 |
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| | | * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 2 | -44/+113 |
| | | * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 3 | -26/+89 |
| | | * | Add hack for handling SVA labels via Verific | Clifford Wolf | 2019-03-07 | 1 | -1/+14 |
| | * | | Update help message for -chparam | Eddie Hung | 2019-03-09 | 1 | -1/+2 |
| | * | | Add -chparam option to verific command | Eddie Hung | 2019-03-09 | 1 | -2/+18 |
| | * | | Fix spelling | Eddie Hung | 2019-03-09 | 1 | -1/+1 |
| | * | | Fix handling of task output ports in clocked always blocks, fixes #857 | Clifford Wolf | 2019-03-07 | 1 | -15/+18 |
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| | * | Merge pull request #848 from YosysHQ/clifford/fix763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
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| | | * | Fix error for wire decl in always block, fixes #763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
| | * | | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 2 | -0/+20 |
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| | * | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| | * | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 |
| | * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 2 | -0/+13 |
| | * | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | * | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | * | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| | * | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 2 | -9/+12 |
| | * | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 |
| | * | Fix segfault in printing of some internal error messages | Clifford Wolf | 2019-02-21 | 1 | -2/+2 |
| * | | Add author name | Eddie Hung | 2019-03-19 | 1 | -0/+1 |
| * | | Fix for using POSIX basename | Eddie Hung | 2019-02-19 | 1 | -2/+4 |
| * | | Missing OSX headers? | Eddie Hung | 2019-02-17 | 1 | -0/+5 |
| * | | read_aiger to ignore line after ands for ascii, not binary | Eddie Hung | 2019-02-17 | 1 | -2/+1 |
| * | | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-02-17 | 1 | -5/+4 |
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| | * | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 |
| * | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger | Eddie Hung | 2019-02-12 | 1 | -3/+1 |
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| | * | | Do not break for constraints | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
| | * | | No increment line_count for binary ANDs | Eddie Hung | 2019-02-11 | 1 | -1/+1 |
| | * | | Do not ignore newline after AND in binary AIG | Eddie Hung | 2019-02-11 | 1 | -1/+0 |
| * | | | Use module->add{Not,And}Gate() functions | Eddie Hung | 2019-02-12 | 1 | -8/+2 |
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| * | | addDff -> addDffGate as per @daveshah1 | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
| * | | Fix tabulation | Eddie Hung | 2019-02-08 | 1 | -28/+28 |
| * | | -module_name arg to go before -clk_name | Eddie Hung | 2019-02-08 | 1 | -7/+7 |
| * | | Add missing "[options]" to read_blif help | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
| * | | Allow module name to be determined by argument too | Eddie Hung | 2019-02-08 | 2 | -14/+44 |
| * | | Refactor into AigerReader class | Eddie Hung | 2019-02-08 | 2 | -79/+92 |
| * | | Parse binary AIG files | Eddie Hung | 2019-02-08 | 1 | -49/+164 |
| * | | Refactor to parse_aiger_header() | Eddie Hung | 2019-02-08 | 1 | -26/+32 |
| * | | Add comment | Eddie Hung | 2019-02-08 | 1 | -0/+1 |
