iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add check for valid macro names in macro definitions	Clifford Wolf	2019-11-07	1	-7/+11
*	Add "verilog_defines -list" and "verilog_defines -reset"	Clifford Wolf	2019-10-21	1	-0/+16
*	Use "(id)" instead of "id" for types as temporary hack	Clifford Wolf	2019-10-14	1	-11/+69
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\| *	sv: Disambiguate interface ports	David Shah	2019-10-03	1	-3/+19
\| *	sv: Fix memories of typedefs	David Shah	2019-10-03	1	-1/+1
\| *	sv: Add %expect	David Shah	2019-10-03	1	-0/+1
\| *	sv: Add support for memory typedefs	David Shah	2019-10-03	1	-1/+19
\| *	sv: Fix typedef parameters	David Shah	2019-10-03	1	-4/+17
\| *	sv: Switch parser to glr, prep for typedef	David Shah	2019-10-03	1	-4/+34
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*	Fix handling of z_digit "?" and fix optimization of cmp with "z"	Clifford Wolf	2019-09-13	1	-5/+1
*	Fix lexing of integer literals without radix	Clifford Wolf	2019-09-13	1	-1/+1
*	Fix lexing of integer literals, fixes #1364	Clifford Wolf	2019-09-12	2	-3/+3
*	substr() -> compare()	Eddie Hung	2019-08-07	1	-4/+4
*	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-07	1	-12/+12
*	verilog_lexer: Increase YY_BUF_SIZE to 65536	David Shah	2019-07-26	1	-0/+3
*	Merge pull request #1147 from YosysHQ/clifford/fix1144	Clifford Wolf	2019-07-03	1	-81/+14
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\| *	Some cleanups in "ignore specify parser"	Clifford Wolf	2019-07-03	1	-79/+5
\| *	Improve specify dummy parser, fixes #1144	Clifford Wolf	2019-06-28	1	-2/+9
* \|	Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...	Clifford Wolf	2019-07-02	1	-0/+2
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*	Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131	Clifford Wolf	2019-06-26	1	-1/+1
*	Merge pull request #1119 from YosysHQ/eddie/fix1118	Clifford Wolf	2019-06-21	1	-0/+1
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\| *	Make genvar a signed type	Eddie Hung	2019-06-20	1	-0/+1
* \|	Maintain "is_unsized" state of constants	Eddie Hung	2019-06-20	1	-6/+6
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*	Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...	Clifford Wolf	2019-06-20	1	-1/+7
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\| *	Unpacked array declaration using size	Tobias Wölfel	2019-06-19	1	-1/+7
* \|	Add "read_verilog -pwires" feature, closes #1106	Clifford Wolf	2019-06-19	2	-3/+15
* \|	Add defaultvalue attribute	Clifford Wolf	2019-06-19	1	-0/+11
* \|	Fix handling of "logic" variables with initial value	Clifford Wolf	2019-06-19	1	-2/+2
* \|	Fixed brojen $error()/$info/$warning() on non-generate blocks	Udi Finkelstein	2019-06-11	2	-3/+13
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*	Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...	Clifford Wolf	2019-06-07	2	-1/+15
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\| *	Initial implementation of elaboration system tasks	Udi Finkelstein	2019-05-03	2	-1/+15
* \|	Cleanup tux3-implicit_named_connection	Clifford Wolf	2019-06-07	1	-1/+1
* \|	Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...	Clifford Wolf	2019-06-07	1	-1/+10
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\| * \|	SystemVerilog support for implicit named port connections	tux3	2019-06-06	1	-9/+17
* \| \|	Fixed memory leak.	Maciej Kurc	2019-06-05	1	-0/+4
* \| \|	Added support for parsing attributes on port connections.	Maciej Kurc	2019-05-31	1	-10/+10
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* \|	Merge branch 'master' into wandwor	Stefan Biereigel	2019-05-27	2	-9/+19
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\| * \|	Added support for unsized constants, fixes #1022	Miodrag Milanovic	2019-05-27	2	-9/+19
* \| \|	fix indentation across files	Stefan Biereigel	2019-05-23	1	-2/+2
* \| \|	make lexer/parser aware of wand/wor net types	Stefan Biereigel	2019-05-23	2	-1/+9
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* \|	Read bigger Verilog files.	Kaj Tuomi	2019-05-18	1	-1/+1
* \|	Merge pull request #1013 from antmicro/parameter_attributes	Clifford Wolf	2019-05-16	1	-2/+2
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\| * \|	Added support for parsing attributes on parameters in Verilog frontent. Conte...	Maciej Kurc	2019-05-16	1	-2/+2
* \| \|	Make the generated *.tab.hh include all the headers needed to define the union.	Henner Zeller	2019-05-14	1	-1/+9
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* \|	Merge pull request #946 from YosysHQ/clifford/specify	Clifford Wolf	2019-05-06	4	-33/+328
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\| * \	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	Clifford Wolf	2019-05-06	2	-2/+10
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\| * \ \	Merge remote-tracking branch 'origin/master' into clifford/specify	Eddie Hung	2019-05-03	1	-2/+2
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\| * \| \|	Improve $specrule interface	Clifford Wolf	2019-04-23	2	-9/+19
\| * \| \|	Improve $specrule interface	Clifford Wolf	2019-04-23	1	-20/+18
\| * \| \|	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	2	-2/+78