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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-26 11:09:43 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-26 11:09:43 +0200 |
| commit | f6053b88103bfc652dec1959f30bfb1880613f61 (patch) | |
| tree | d18e48773a2472de67920ea804252c9ad82f0d15 /frontends/verilog | |
| parent | 8e9ef891febb47f512710de591401539ad521634 (diff) | |
| download | yosys-f6053b88103bfc652dec1959f30bfb1880613f61.tar.gz yosys-f6053b88103bfc652dec1959f30bfb1880613f61.tar.bz2 yosys-f6053b88103bfc652dec1959f30bfb1880613f61.zip | |
Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 3a3634d34..f6a17b242 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -153,7 +153,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { if (warn_z) { AstNode *ret = const2ast(code, case_type); - if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) + if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num()); return ret; |