iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-0/+2
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-2/+2
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	1	-6/+2
*	Implemented indexed part selects	Clifford Wolf	2013-11-20	1	-0/+3
*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20	1	-6/+6
*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21	1	-0/+2
*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20	1	-1/+1
*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19	1	-1/+1
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-1/+2
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-2/+2
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	1	-0/+1
*	Added support for verilog === operator	Clifford Wolf	2013-05-07	1	-0/+2
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-1/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+264