iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-3/+1
*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	2	-1/+19
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	3	-34/+16
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	3	-10/+17
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24	1	-1/+3
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	2	-5/+35
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-0/+3
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	3	-3/+3
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	3	-1/+17
*	initial import	Clifford Wolf	2013-01-05	5	-0/+3227