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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-23 18:54:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-23 18:54:31 +0100 |
| commit | e45d1c8865d97dfd6a671bc09cdaf6f69d700f37 (patch) | |
| tree | a869410bbd7d7bb4de001804563e3504de98c4a1 /frontends/ast | |
| parent | bee57c808acb33b893cef034856861bb20b99588 (diff) | |
| download | yosys-e45d1c8865d97dfd6a671bc09cdaf6f69d700f37.tar.gz yosys-e45d1c8865d97dfd6a671bc09cdaf6f69d700f37.tar.bz2 yosys-e45d1c8865d97dfd6a671bc09cdaf6f69d700f37.zip | |
Tiny fixes to verilog parser
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/simplify.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index feb810674..94423366e 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -120,6 +120,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage) if (node->type == AST_WIRE) { if (this_wire_scope.count(node->str) > 0) { AstNode *first_node = this_wire_scope[node->str]; + if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0) + goto wires_are_compatible; if (first_node->children.size() != node->children.size()) goto wires_are_incompatible; for (size_t j = 0; j < node->children.size(); j++) { @@ -138,6 +140,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage) goto wires_are_incompatible; if (first_node->port_id == 0 && (node->is_input || node->is_output)) goto wires_are_incompatible; + wires_are_compatible: if (node->is_input) first_node->is_input = true; if (node->is_output) |