iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-45/+45
*	Merge pull request #1718 from boqwxp/precise_locations	Claire Wolf	2020-03-03	1	-102/+101
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\| *	Closes #1717. Add more precise Verilog source location information to AST and...	Alberto Gonzalez	2020-02-23	1	-102/+101
* \|	ast: fixes #1710; do not generate RTLIL for unreachable ternary	Eddie Hung	2020-02-27	1	-9/+22
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*	Merge pull request #1703 from YosysHQ/eddie/specify_improve	Eddie Hung	2020-02-21	1	-7/+11
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\| *	verilog: fix $specify3 check	Eddie Hung	2020-02-13	1	-7/+11
* \|	partial rebase of PeterCrozier's enum work onto current master	Jeff Wang	2020-01-16	1	-2/+6
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*	sv: Switch parser to glr, prep for typedef	David Shah	2019-10-03	1	-0/+1
*	substr() -> compare()	Eddie Hung	2019-08-07	1	-1/+1
*	genrtlil: emit \src attribute on CaseRule.	whitequark	2019-07-08	1	-0/+1
*	Add "read_verilog -pwires" feature, closes #1106	Clifford Wolf	2019-06-19	1	-1/+20
*	Fixes and cleanups in AST_TECALL handling	Clifford Wolf	2019-06-07	1	-1/+31
*	Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...	Clifford Wolf	2019-06-07	1	-0/+1
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\| *	Initial implementation of elaboration system tasks	Udi Finkelstein	2019-05-03	1	-0/+1
* \|	Merge branch 'master' into wandwor	Stefan Biereigel	2019-05-27	1	-3/+9
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\| * \	Merge pull request #1044 from mmicko/invalid_width_range	Clifford Wolf	2019-05-27	1	-1/+2
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\| \| * \|	Give error instead of asserting for invalid range, fixes #947	Miodrag Milanovic	2019-05-27	1	-1/+2
\| * \| \|	Added support for unsized constants, fixes #1022	Miodrag Milanovic	2019-05-27	1	-2/+7
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* \| \|	move wand/wor resolution into hierarchy pass	Stefan Biereigel	2019-05-27	1	-97/+14
* \| \|	fix assignment of non-wires	Stefan Biereigel	2019-05-23	1	-16/+19
* \| \|	fix indentation across files	Stefan Biereigel	2019-05-23	1	-58/+76
* \| \|	implementation for assignments working	Stefan Biereigel	2019-05-23	1	-14/+79
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* \|	Improve write_verilog specify support	Clifford Wolf	2019-05-04	1	-0/+3
* \|	Merge remote-tracking branch 'origin/master' into clifford/specify	Eddie Hung	2019-05-03	1	-0/+2
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\| * \|	Fix width detection of memory access with bit slice, fixes #974	Clifford Wolf	2019-05-01	1	-0/+2
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* \|	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	1	-0/+6
* \|	Checking and fixing specify cells in genRTLIL	Clifford Wolf	2019-04-23	1	-1/+15
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*	Improve handling of "full_case" attributes	Clifford Wolf	2019-03-14	1	-0/+9
*	Add support for SVA labels in read_verilog	Clifford Wolf	2019-03-07	1	-3/+9
*	Fix error for wire decl in always block, fixes #763	Clifford Wolf	2019-03-02	1	-1/+5
*	Fixes related to handling of autowires and upto-ranges, fixes #814	Clifford Wolf	2019-02-21	1	-2/+2
*	Fix segfault in printing of some internal error messages	Clifford Wolf	2019-02-21	1	-2/+2
*	Fix sign handling of real constants	Clifford Wolf	2019-02-13	1	-5/+4
*	Various indenting fixes in AST front-end (mostly space vs tab issues)	Clifford Wolf	2018-11-04	1	-55/+33
*	Improve read_verilog range out of bounds warning	Clifford Wolf	2018-10-20	1	-6/+6
*	Refactor code to avoid code duplication + added comments	Ruben Undheim	2018-10-20	1	-21/+4
*	Documentation improvements etc.	Ruben Undheim	2018-10-13	1	-5/+7
*	Support for 'modports' for System Verilog interfaces	Ruben Undheim	2018-10-12	1	-0/+29
*	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-2/+46
*	Fix for issue 594.	Tom Verbeure	2018-10-02	1	-1/+2
*	Convert more log_error() to log_file_error() where possible.	Henner Zeller	2018-07-20	1	-71/+69
*	Use log_file_warning(), log_file_error() functions.	Henner Zeller	2018-07-20	1	-16/+16
*	Provide source-location logging.	Henner Zeller	2018-07-19	1	-3/+2
*	Fix handling of signed memories	Clifford Wolf	2018-06-28	1	-0/+3
*	Add (* gclk *) attribute support	Clifford Wolf	2018-06-01	1	-0/+9
*	Add $allconst and $allseq cell types	Clifford Wolf	2018-02-23	1	-2/+2
*	Fix error handling for nested always/initial	Clifford Wolf	2017-12-02	1	-0/+2
*	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...	Clifford Wolf	2017-06-07	1	-0/+7
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-1/+6
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-0/+2