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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-05-27 12:25:18 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-05-27 12:25:18 +0200 |
| commit | 84ffb217081fed7ddf1f683f65f2a2fdf813cd6b (patch) | |
| tree | 69f29d913022723d40eb342e52678baf9e36b536 /frontends/ast/genrtlil.cc | |
| parent | 2058c7c53bed0d2536b6962855271cd7229fbd52 (diff) | |
| download | yosys-84ffb217081fed7ddf1f683f65f2a2fdf813cd6b.tar.gz yosys-84ffb217081fed7ddf1f683f65f2a2fdf813cd6b.tar.bz2 yosys-84ffb217081fed7ddf1f683f65f2a2fdf813cd6b.zip | |
Give error instead of asserting for invalid range, fixes #947
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 379fed641..1b19ba4e5 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -904,7 +904,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!range_valid) log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str()); - log_assert(range_left >= range_right || (range_left == -1 && range_right == 0)); + if (!(range_left >= range_right || (range_left == -1 && range_right == 0))) + log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); |