| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -3/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 1 | -1/+0 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 1 | -1/+3 |
| |\ | | | | | | | clifford/pr983 | ||||
| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -1/+3 |
| | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | ||||
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 1 | -1/+3 |
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| | * | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+3 |
| | |/ | | | | | | | Includes work from @sumit0190 and @AaronKel | ||||
| * | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 1 | -1/+0 |
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| * | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 1 | -1/+1 |
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| * | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 1 | -0/+1 |
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| * | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 1 | -1/+1 |
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| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -0/+5 |
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+3 |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+6 |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | ||||
| * | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -2/+2 |
| | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. | ||||
| * | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -4/+4 |
| |\ | | | | | Consistent use of 'override' for virtual methods in derived classes. | ||||
| | * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -4/+4 |
| | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+1 |
| |\ \ | |/ |/| | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | ||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -1/+1 |
| | | | | | | | | | No longer false warnings for memories and assertions | ||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | ||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 1 | -7/+7 |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+2 |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+1 |
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| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 1 | -0/+1 |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+0 |
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| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -1/+1 |
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| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 1 | -3/+5 |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+1 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+1 |
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| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -1/+3 |
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| * | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 1 | -0/+1 |
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| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -0/+2 |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
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| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+1 |
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| * | Fixed nested mem2reg | Clifford Wolf | 2015-07-29 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -0/+1 |
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| * | Added "read_verilog -nomeminit" and "nomeminit" attribute | Clifford Wolf | 2015-02-14 | 1 | -3/+3 |
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| * | Creating $meminit cells in verilog front-end | Clifford Wolf | 2015-02-14 | 1 | -1/+2 |
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| * | dict/pool changes in ast | Clifford Wolf | 2014-12-29 | 1 | -4/+8 |
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| * | Changed more code to dict<> and pool<> | Clifford Wolf | 2014-12-28 | 1 | -2/+2 |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
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| * | Added support for $readmemh/$readmemb | Clifford Wolf | 2014-10-26 | 1 | -0/+1 |
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| * | Fixed handling of invalid array access in mem2reg code | Clifford Wolf | 2014-10-16 | 1 | -0/+1 |
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