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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-03 15:25:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-03 15:25:59 +0200 |
| commit | a572b495387743a58111e7264917a497faa17ebf (patch) | |
| tree | 103a3523b1868e31ec88d9b56ceb750f824bf487 /frontends/ast/ast.h | |
| parent | e060375f23d56b4e330a946d5a626f0163499618 (diff) | |
| download | yosys-a572b495387743a58111e7264917a497faa17ebf.tar.gz yosys-a572b495387743a58111e7264917a497faa17ebf.tar.bz2 yosys-a572b495387743a58111e7264917a497faa17ebf.zip | |
Replace -ignore_redef with -[no]overwrite
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d1e2c78d1..756629aca 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -275,7 +275,7 @@ namespace AST // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, - bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions |