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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:40:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:40:17 +0200 |
| commit | a7b07696238dbfd8e4fb5fd41d597200abef4909 (patch) | |
| tree | b4416478dfad389f247b49f3f528803f838c2421 /frontends/ast/ast.h | |
| parent | 8537c4d2061db1ee11defc357781c6c534be5b3d (diff) | |
| download | yosys-a7b07696238dbfd8e4fb5fd41d597200abef4909.tar.gz yosys-a7b07696238dbfd8e4fb5fd41d597200abef4909.tar.bz2 yosys-a7b07696238dbfd8e4fb5fd41d597200abef4909.zip | |
Added "read_verilog -dump_rtlil"
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 5310bcadb..530c11ba5 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -187,7 +187,7 @@ namespace AST int linenum; // creating and deleting nodes - AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL); + AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL); AstNode *clone(); void cloneInto(AstNode *other); void delete_children(); @@ -272,7 +272,8 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, + bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions @@ -302,7 +303,8 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; + extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map<std::string, AST::AstNode*> current_scope; extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; |