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* cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.whitequark2020-06-072-1/+1
* cxxrtl: add a C API for writing VCD dumps.whitequark2020-06-075-2/+204
* cxxrtl: only write VCD values that were actually updated.whitequark2020-06-071-10/+30
* cxxrtl: add a VCD writer using debug information.whitequark2020-06-071-0/+194
* cxxrtl: add a C API for driving and introspecting designs.whitequark2020-06-064-29/+291
* cxxrtl: generate debug information for non-localized public wires.whitequark2020-06-062-2/+131
* Merge pull request #2110 from BracketMaster/masterwhitequark2020-06-061-1/+1
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| * more reasonable numbers for memoryYehowshua Immanuel2020-06-041-1/+1
| * MacOS has even stricter stack limits in catalina.Yehowshua Immanuel2020-06-041-1/+1
* | Merge pull request #2113 from whitequark/cxxrtl-fix-sshrwhitequark2020-06-051-1/+1
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| * | cxxrtl: fix implementation of $sshr cell.whitequark2020-06-051-1/+1
* | | Merge pull request #2109 from nakengelhardt/btor_internal_namesN. Engelhardt2020-06-051-5/+5
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| * | btor backend: make not printing internal names defaultN. Engelhardt2020-06-041-5/+5
* | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-28/+22
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| * | xaiger: cleanupEddie Hung2020-05-251-28/+22
* | | Add printf format attributes to btorf/infof helper functionsClaire Wolf2020-06-041-3/+3
* | | btor backend: add option to not include internal namesN. Engelhardt2020-06-041-33/+42
* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-042-0/+6
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| * | | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-272-0/+6
* | | | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-1/+1
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| * | | xaiger: promote abc9_keep wiresEddie Hung2020-05-251-1/+1
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* | | Merge pull request #2018 from boqwxp/qbfsat-timeoutclairexen2020-05-302-5/+31
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| * | | smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.Alberto Gonzalez2020-05-291-4/+0
| * | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, a...Alberto Gonzalez2020-05-252-5/+35
* | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-297-9/+116
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| * | | | Add flooring division operatorXiretza2020-05-283-3/+58
| * | | | Add flooring modulo operatorXiretza2020-05-287-9/+61
* | | | | Merge pull request #2016 from boqwxp/qbfsat-yicesclairexen2020-05-291-1/+5
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| * | | qbfsat: Move SMT2 info statements back to the top of the file.Alberto Gonzalez2020-05-251-3/+3
| * | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices th...Alberto Gonzalez2020-05-251-3/+7
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* | | Merge pull request #2031 from epfl-vlsc/masterwhitequark2020-05-281-1/+40
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| * | | Formatting fixesSahand Kashani2020-05-061-14/+7
| * | | Add extmodule support to firrtl backendSahand Kashani2020-05-061-1/+47
* | | | Merge pull request #2063 from boqwxp/techmapped-firrtlwhitequark2020-05-281-10/+12
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| * | | | firrtl: Accept techmapped cell types in FIRRTL backend.Alberto Gonzalez2020-05-171-10/+12
* | | | | cxxrtl: make logging a little bit nicer.whitequark2020-05-261-2/+10
* | | | | cxxrtl: add missing parts of commit 281c9685.whitequark2020-05-261-5/+3
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* | | | xaiger: do not derive cellsEddie Hung2020-05-241-7/+1
* | | | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.whitequark2020-05-221-8/+2
* | | | Merge pull request #2054 from boqwxp/fix-smtbmcN. Engelhardt2020-05-201-3/+3
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| * | | | smtbmc: Fix typo in error message.Alberto Gonzalez2020-05-191-1/+1
| * | | | smtbmc: Fix return status handling.Alberto Gonzalez2020-05-141-2/+2
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* | | | abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-141-5/+5
* | | | abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-141-40/+32
* | | | Cleanup; reduce Module::derive() callsEddie Hung2020-05-141-18/+20
* | | | xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarityEddie Hung2020-05-141-16/+5
* | | | abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-141-0/+1
* | | | Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"Eddie Hung2020-05-141-4/+0
* | | | xaiger: always sort input/output bits by port idEddie Hung2020-05-141-12/+10
* | | | abc9: generate $abc9_holes design instead of <name>$holesEddie Hung2020-05-141-3/+9
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