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* write_xaiger: inherit port ordering from original moduleEddie Hung2019-12-271-5/+16
* Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"Eddie Hung2019-12-271-19/+27
* Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-271-27/+19
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| * Revert "write_xaiger: only instantiate each whitebox cell type once"David Shah2019-12-271-27/+19
* | write_xaiger: simplify c{i,o}_bitsEddie Hung2019-12-271-12/+6
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* write_xaiger: only instantiate each whitebox cell type onceEddie Hung2019-12-201-19/+27
* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-24/+21
* Stray newlineEddie Hung2019-12-061-1/+0
* write_xaiger to inst each cell type once, do not call techmap/aigmapEddie Hung2019-12-061-21/+25
* Revert "Fold loop"Eddie Hung2019-11-271-3/+6
* latch -> boxEddie Hung2019-11-261-1/+1
* Fold loopEddie Hung2019-11-261-6/+3
* Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1
* xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
* write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
* Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
* Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
* Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
* Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
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| * write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
* | Bugfix in smtio vcd handling of $-identifiersClifford Wolf2019-10-231-6/+9
* | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-9/+9
* | Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
* | Fix btor back-end to use "state" instead of "input" for undef init bitsClifford Wolf2019-10-021-6/+9
* | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-291-8/+8
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| * | "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-1/+6
| * | Force $inout.out ports to begin with '$' to indicate internalEddie Hung2019-09-231-1/+1
| * | When two boxes connect to each other, need not be a (* keep *)Eddie Hung2019-09-191-6/+1
* | | Merge pull request #1413 from YosysHQ/mmicko/backend_binary_outMiodrag Milanović2019-09-293-4/+4
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| * | | Add aiger and protobuf backends binary supportMiodrag Milanovic2019-09-282-3/+3
| * | | Support binary files for backends, fixes #1407Miodrag Milanovic2019-09-281-1/+1
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* / / Corrects btor2 backendAman Goel2019-09-271-1/+4
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* | Add "write_aiger -L"Clifford Wolf2019-09-181-5/+16
* | Fix stupid bug in btor back-endClifford Wolf2019-09-181-1/+1
* | backends: smt2: use $(CXX) variable for compilerSean Cross2019-09-081-1/+1
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* Recognise built-in types (e.g. $_DFF_*)Eddie Hung2019-08-301-3/+3
* Revert "Revert "Fix omode which inserts an output if none exists (otherwise a...Eddie Hung2019-08-281-7/+8
* Revert "Output "h" extension only if boxes"Eddie Hung2019-08-281-32/+28
* Output "h" extension only if boxesEddie Hung2019-08-211-28/+32
* Revert "Fix omode which inserts an output if none exists (otherwise abc9 brea...Eddie Hung2019-08-211-8/+7
* Fix omode which inserts an output if none exists (otherwise abc9 breaks)Eddie Hung2019-08-201-7/+8
* Revert "Only xaig if GetSize(output_bits) > 0"Eddie Hung2019-08-201-149/+147
* Only xaig if GetSize(output_bits) > 0Eddie Hung2019-08-201-147/+149
* Remove sequential extensionEddie Hung2019-08-201-270/+29
* Do not sigmap!Eddie Hung2019-08-201-2/+2
* Minor refactorEddie Hung2019-08-201-7/+6
* Output i/o/h extensions even if no boxes or flopsEddie Hung2019-08-191-65/+66
* Add (* abc_arrival *) attributeEddie Hung2019-08-191-9/+66
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-191-1/+1
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| * Fix various NDEBUG compiler warnings, closes #1255Clifford Wolf2019-08-131-1/+1