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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:40 -0700 |
| commit | 44374b1b2b0dbc455c9e43d713e133d7d78a5e1a (patch) | |
| tree | 7e2b502d6272e72fcd8de886a9af08d684805cc0 /backends | |
| parent | c340fbfab23c582103402bbd812d9bca4510dc41 (diff) | |
| download | yosys-44374b1b2b0dbc455c9e43d713e133d7d78a5e1a.tar.gz yosys-44374b1b2b0dbc455c9e43d713e133d7d78a5e1a.tar.bz2 yosys-44374b1b2b0dbc455c9e43d713e133d7d78a5e1a.zip | |
"abc_padding" attr for blackbox outputs that were padded, remove them later
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 21b281708..5e49f3c80 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -350,6 +350,8 @@ struct XAigerWriter if (!box_module || !box_module->attributes.count("\\abc_box_id")) continue; + bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); + // Fully pad all unused input connections of this box cell with S0 // Fully pad all undriven output connections of this box cell with anonymous wires // NB: Assume box_module->ports are sorted alphabetically @@ -394,7 +396,10 @@ struct XAigerWriter rhs = it->second; } else { - rhs = module->addWire(NEW_ID, GetSize(w)); + Wire *wire = module->addWire(NEW_ID, GetSize(w)); + if (blackbox) + wire->set_bool_attribute(ID(abc_padding)); + rhs = wire; cell->setPort(port_name, rhs); } |