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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-302-1/+17
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| * Added $initstate support to smtbmc flowClifford Wolf2016-07-272-1/+17
* | Added "write_verilog -defparam"Clifford Wolf2016-07-301-2/+21
* | Added "write_verilog -nodec -nostr"Clifford Wolf2016-07-301-4/+27
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* write_json: also write module attributes.whitequark2016-07-121-2/+6
* Yosys-smtbmc: Support for hierarchical VCD dumpingClifford Wolf2016-07-112-23/+59
* Moved smt2 yosys info parsing from smtbmc.py to smtio.pyClifford Wolf2016-07-113-16/+56
* Support for hierarchical designs in smt2 back-endClifford Wolf2016-07-102-24/+144
* Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behaviorClifford Wolf2016-07-081-13/+15
* In BLIF, a .names without entries already always outputs 0Clifford Wolf2016-07-081-11/+0
* Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddie...Clifford Wolf2016-07-081-2/+19
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| * Fix for all zero maskeddiehung2015-05-031-0/+11
| * Escape '<' and '>' some moreeddiehung2015-05-031-1/+1
| * For vtr, escape angle brackets as welleddiehung2015-04-281-1/+1
| * blifwriter: write out .names for true/false/undef type == '-'eddiehung2015-04-281-0/+6
* | Added $sop support to BLIF back-endClifford Wolf2016-06-181-2/+29
* | Also escape "=" in spice outputClifford Wolf2016-05-201-1/+1
* | Added "write_blif -noalias"Clifford Wolf2016-05-061-6/+26
* | Added support for "active high" and "active low" latches in BLIF back-endClifford Wolf2016-04-221-0/+12
* | Added "yosys -D" featureClifford Wolf2016-04-2110-11/+11
* | Fixed some typosClifford Wolf2016-04-053-3/+3
* | Renamed opt_const to opt_exprClifford Wolf2016-03-311-1/+1
* | Bugfix in write_verilog for RTLIL processesClifford Wolf2016-03-141-9/+20
* | Added "write_edif -nogndvcc"Clifford Wolf2016-03-081-17/+34
* | Be more conservative with net names in spice outputClifford Wolf2016-03-021-18/+47
* | user-facing spelling fixesSebastian Kuzminsky2016-02-281-3/+3
* | Added "int ceil_log2(int)" functionClifford Wolf2016-02-131-8/+8
* | Added "write_blif -cname" modeClifford Wolf2016-01-061-1/+12
* | Added yosys-smtbmc -SClifford Wolf2015-12-201-6/+35
* | Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-252-7/+7
* | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-2/+2
* | Progress in yosys-smtbmcClifford Wolf2015-10-151-4/+10
* | Improvements in yosys-smtbmcClifford Wolf2015-10-153-2/+9
* | More "yosys-smtbmc -c" fixesClifford Wolf2015-10-142-9/+30
* | Fixed yosys-smtbmc -cClifford Wolf2015-10-141-2/+2
* | Added yosys-smtbmc copyrightClifford Wolf2015-10-143-1/+36
* | Improvements in yosys-smtbmcClifford Wolf2015-10-143-21/+38
* | Added yosys-smtbmcClifford Wolf2015-10-142-1/+20
* | Implemented smtbmc.py -iClifford Wolf2015-10-141-25/+60
* | Added smtbmc.pyClifford Wolf2015-10-134-0/+409
* | Added write_smt2 -wiresClifford Wolf2015-10-131-7/+15
* | Bugfixes in writing of memories as VerilogClifford Wolf2015-09-251-7/+8
* | Added "yosys-smt2-wire" tag support to smt2 back-endClifford Wolf2015-08-311-0/+2
* | Fixed generation of smt2 concat statementsClifford Wolf2015-08-151-3/+5
* | Another block of spelling fixesLarry Doolittle2015-08-143-4/+4
* | Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-3/+3
* | Spell check (by Larry Doolittle)Clifford Wolf2015-08-142-3/+3
* | Added "write_smt2 -regs"Clifford Wolf2015-08-121-7/+36
* | Added SMV back-end 'test_cells.sh' scriptClifford Wolf2015-08-121-0/+33
* | Use MEMID as name for $mem cellClifford Wolf2015-08-091-1/+6
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