Another block of spelling fixes

Smaller this time

3 files changed, 4 insertions, 4 deletions

diff --git a/backends/btor/verilog2btor.sh b/backends/btor/verilog2btor.sh
index cfdc066a8..1c537d5bd 100755
--- a/backends/btor/verilog2btor.sh
+++ b/backends/btor/verilog2btor.sh
@@ -1,7 +1,7 @@
 #!/bin/sh
 
 #
-# Script to writing btor from verilog design
+# Script to write BTOR from Verilog design
 #
 
 if [ "$#" -ne 3 ]; then
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 388251e35..9bc936a6c 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -329,7 +329,7 @@ struct JsonBackend : public Backend {
 		log("connected to a constant driver are denoted as string \"0\" or \"1\" instead of\n");
 		log("a number.\n");
 		log("\n");
-		log("For example the following verilog code:\n");
+		log("For example the following Verilog code:\n");
 		log("\n");
 		log("    module test(input x, y);\n");
 		log("      (* keep *) foo #(.P(42), .Q(1337))\n");
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 28c54ce0b..c04389f63 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -17,7 +17,7 @@
  *
  *  ---
  *
- *  A simple and straightforward verilog backend.
+ *  A simple and straightforward Verilog backend.
  *
  *  Note that RTLIL processes can't always be mapped easily to a Verilog
  *  process. Therefore this frontend should only be used to export a
@@ -966,7 +966,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 				n += wen_width;
 			}
 		}
-		// Output verilog that looks something like this:
+		// Output Verilog that looks something like this:
 		// reg [..] _3_;
 		// always @(posedge CLK2) begin
 		//   _3_ <= memory[D1ADDR];