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* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
* Minor style fixesClifford Wolf2018-12-182-1/+1
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
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| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
* | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
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| * | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
* | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
* | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
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* Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
* Merge pull request #693 from YosysHQ/rlimitClifford Wolf2018-11-071-8/+11
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| * Limit stack size to 16 MB on DarwinClifford Wolf2018-11-071-1/+4
| * Fix for improved smtio.py rlimit codeClifford Wolf2018-11-061-1/+1
| * Improve stack rlimit code in smtio.pyClifford Wolf2018-11-061-8/+8
* | Run solver in non-incremental mode whem smtio.py is configured for non-increm...Clifford Wolf2018-11-061-3/+12
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* Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
* Add proper error message for when smtbmc "append" failsClifford Wolf2018-11-041-2/+10
* Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
* adding offset info to memoriesrafaeltp2018-10-181-1/+1
* adding offset info to memoriesrafaeltp2018-10-181-2/+3
* Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
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| * Minor updateAman Goel2018-10-151-1/+1
| * Update to .smv backendAman Goel2018-10-011-33/+52
* | Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
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* added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
* Fixed typo in "verilog_write" help messageacw12512018-09-181-3/+3
* Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
* Remove unused functions.Jim Lawson2018-08-271-10/+0
* Add support for module instances.Jim Lawson2018-08-231-17/+122
* Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-1515-36/+36
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| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2015-36/+36
* | Merge pull request #576 from cr1901/no-resourceClifford Wolf2018-08-151-9/+12
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| * | Gate POSIX-only signals and resource module to only run on POSIX Python imple...William D. Jones2018-07-061-9/+12
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* | Fix use of signed integers in JSON back-endClifford Wolf2018-08-141-1/+3
* | Use `realpath` jpathy2018-08-061-1/+1
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* Fix protobuf buildSergiusz Bazanski2018-06-201-1/+1
* Add Protobuf backendSerge Bazanski2018-06-193-0/+380
* Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
* Add "write_blif -inames -iattr"Clifford Wolf2018-04-151-22/+46
* Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constantsClifford Wolf2018-04-041-0/+3
* Fixed -stbv handling in SMT2 back-endClifford Wolf2018-04-041-1/+1
* Add smtio status msgs when --progress is inactiveClifford Wolf2018-03-291-2/+23
* Bugfix in smtio.py VCD file generatorClifford Wolf2018-03-291-1/+1
* Add $mem support to SMT2 clock taggingClifford Wolf2018-03-271-0/+18
* Improve yosys-smtbmc log output and error handlingClifford Wolf2018-03-171-5/+14
* Improve handling of invalid check-sat result in smtio.pyClifford Wolf2018-03-171-1/+2
* Remove debug prints from yosys-smtbmc VCD writerClifford Wolf2018-03-081-2/+0
* Check results of (check-sat) in yosys-smtbmcClifford Wolf2018-03-071-0/+2
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