iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	opt_expr: simplify any unsigned comparisons with all-0 and all-1.	whitequark	2019-01-02	3	-17/+84
*	Merge pull request #768 from whitequark/opt_lut_elim	Clifford Wolf	2019-01-01	4	-0/+104
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\| *	opt_lut: eliminate LUTs evaluating to constants or inputs.	whitequark	2018-12-31	4	-0/+104
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*	Fix handling of (* keep *) wires in wreduce	Clifford Wolf	2018-12-31	1	-1/+4
*	Merge pull request #766 from Icenowy/anlogic-latches	Clifford Wolf	2018-12-31	1	-0/+12
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\| *	anlogic: add latch cells	Icenowy Zheng	2018-12-25	1	-0/+12
* \|	Fix 7 instances of add_share_file to add_gen_share_file	Larry Doolittle	2018-12-29	1	-8/+8
* \|	Squelch a little more trailing whitespace	Larry Doolittle	2018-12-29	2	-4/+4
* \|	Merge pull request #761 from whitequark/proc_clean_partial	Clifford Wolf	2018-12-23	3	-10/+42
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\| * \|	proc_clean: remove any empty cases if all cases use all-def compare.	whitequark	2018-12-23	3	-6/+42
\| * \|	proc_clean: remove any empty cases at the end of the switch.	whitequark	2018-12-22	1	-7/+3
* \| \|	Add "read_ilang -[no]overwrite"	Clifford Wolf	2018-12-23	3	-4/+54
* \| \|	Merge branch 'master' of github.com:YosysHQ/yosys	Clifford Wolf	2018-12-23	7	-22/+58
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\| * \ \	Merge pull request #757 from whitequark/manual_mem	Clifford Wolf	2018-12-22	2	-10/+37
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\| \| * \|	manual: make description of $meminit ports match reality.	whitequark	2018-12-21	1	-3/+15
\| \| * \|	manual: fix typos.	whitequark	2018-12-20	1	-2/+2
\| \| * \|	manual: document $meminit cell and memory_* passes.	whitequark	2018-12-20	2	-8/+23
\| * \| \|	Merge pull request #758 from whitequark/tcl_script_args	Clifford Wolf	2018-12-21	1	-7/+18
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\| \| * \| \|	tcl: add support for passing arguments to scripts.	whitequark	2018-12-20	1	-7/+18
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\| * \| \|	Merge pull request #759 from whitequark/memory_collect_init_x	Clifford Wolf	2018-12-21	1	-3/+0
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\| \| * \|	memory_collect: do not truncate 'x from \INIT.	whitequark	2018-12-21	1	-3/+0
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\| * \|	Merge pull request #752 from Icenowy/anlogic-lut-cost	Clifford Wolf	2018-12-19	1	-1/+1
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\| \| * \|	Anlogic: let LUT5/6 have more cost than LUT4-	Icenowy Zheng	2018-12-19	1	-1/+1
\| * \| \|	Merge pull request #753 from Icenowy/anlogic-makefile-fix	Clifford Wolf	2018-12-19	1	-0/+1
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\| \| * \| \|	anlogic: fix Makefile.inc	Icenowy Zheng	2018-12-19	1	-0/+1
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\| * \| \|	Merge pull request #749 from Icenowy/anlogic-dram-fix	Clifford Wolf	2018-12-19	1	-1/+1
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\| \| * \| \|	anlogic: fix dbits of Anlogic Eagle DRAM16X4	Icenowy Zheng	2018-12-18	1	-1/+1
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* \| / /	Minor style fixes	Clifford Wolf	2018-12-18	2	-1/+1
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* \| \|	Merge pull request #748 from makaimann/add-btor-ops	Clifford Wolf	2018-12-18	2	-2/+38
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\| * \| \|	Add btor ops for $mul, $div, $mod and $concat	makaimann	2018-12-17	2	-2/+38
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* \| \|	Merge pull request #751 from daveshah1/fix_589	Clifford Wolf	2018-12-18	1	-1/+1
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\| * \| \|	memory_dff: Fix typo when checking init value	David Shah	2018-12-18	1	-1/+1
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* \| \|	Fix segfault in AST simplify	Clifford Wolf	2018-12-18	1	-0/+5
* \| \|	Improve src tagging (using names and attrs) of cells and wires in verific fro...	Clifford Wolf	2018-12-18	2	-99/+160
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* \|	Merge pull request #746 from Icenowy/anlogic-dram	Clifford Wolf	2018-12-17	5	-1/+355
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\| *	anlogic: add support for Eagle Distributed RAM	Icenowy Zheng	2018-12-17	4	-1/+43
\| *	Revert "Leave only real black box cells"	Icenowy Zheng	2018-12-17	1	-0/+312
* \|	Merge pull request #742 from whitequark/changelog	Clifford Wolf	2018-12-17	1	-0/+7
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\| * \|	Update CHANGELOG.	whitequark	2018-12-16	1	-0/+7
* \| \|	Merge pull request #741 from whitequark/ilang_slice_sigspec	Clifford Wolf	2018-12-17	1	-10/+6
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\| * \| \|	read_ilang: allow slicing sigspecs.	whitequark	2018-12-16	1	-10/+6
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* \| \|	Merge pull request #744 from whitequark/write_verilog_$shift	Clifford Wolf	2018-12-17	1	-0/+29
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\| * \|	write_verilog: handle the $shift cell.	whitequark	2018-12-16	1	-0/+29
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* \|	Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming	Clifford Wolf	2018-12-16	1	-51/+29
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\| *	Revert "Proof-of-concept: preserve naming through ABC using dress"	Clifford Wolf	2018-12-16	1	-51/+29
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*	Merge pull request #736 from whitequark/select_assert_list	Clifford Wolf	2018-12-16	2	-9/+51
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\| *	select: print selection if a -assert-* flag causes an error.	whitequark	2018-12-16	1	-8/+50
\| *	write_verilog: add a missing newline.	whitequark	2018-12-16	1	-1/+1
* \|	Rename "fine:" label to "map:" in "synth_ice40"	Clifford Wolf	2018-12-16	1	-1/+1
* \|	Merge pull request #704 from webhat/feature/fix-awk	Clifford Wolf	2018-12-16	1	-2/+3
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