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* Add verilog backend option for simple_lhsMiodrag Milanovic2020-11-251-6/+22
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* generate only simple assignments in verilog backendMiodrag Milanovic2020-11-251-5/+9
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* verilog_backend: Use Mem helper.Marcelina Kościelnicka2020-10-211-274/+251
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* write_verilog: emit intermediate wire for constant values in sensitivity listN. Engelhardt2020-09-281-7/+53
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* Respect \A_SIGNED for $shiftXiretza2020-08-181-6/+4
| | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* verilog_backend: Add handling for all FF types.Marcelina Kościelnicka2020-07-301-252/+134
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* verilog_backend: in non-SV mode, add a trigger for `always @*`.whitequark2020-07-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This commit only affects translation of RTLIL processes (for which there is limited support). Due to the event-driven nature of Verilog, processes like reg x; always @* x <= 1; may never execute. This can be fixed in SystemVerilog code by using `always_comb` instead of `always @*`, but in Verilog-2001 the options are limited. This commit implements the following workaround: reg init = 0; reg x; always @* begin if (init) begin end x <= 1; end Fixes #2271.
* verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-161-11/+18
| | | | See #2271.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-0/+55
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-0/+34
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* write_verilog: fix precondition check.whitequark2020-04-141-1/+1
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-221/+221
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* kernel: use more ID::*Eddie Hung2020-04-021-41/+41
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* Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.Alberto Gonzalez2020-04-011-22/+19
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* specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+10
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* write_verilog: dump $mem cell attributes.whitequark2020-02-061-0/+1
| | | | | The Verilog backend already dumps attributes on RTLIL::Memory objects but not on `$mem` cells.
* write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
* write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before.
* substr() -> compare()Eddie Hung2019-08-071-2/+2
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* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-6/+6
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* Use State::S{0,1}Eddie Hung2019-08-061-2/+2
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
|\ | | | | write_verilog: dump zero width constants correctly
| * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again).
* | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
|\ | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
* | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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* verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
| | | | This appears to be an omission.
* verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
| | | | Attributes are not permitted in that position by Verilog grammar.
* Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve write_verilog specify supportClifford Wolf2019-05-041-15/+71
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for zero-width signals to Verilog back-end, fixes #948Clifford Wolf2019-04-221-0/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_verilog -siminit"Clifford Wolf2019-02-281-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| | | | per @cliffordwolf
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-171-38/+41
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| * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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* | RefactorEddie Hung2019-02-061-21/+5
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* | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ | | | | write_verilog: write $tribuf cell as ternary
| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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