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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:18:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:18:18 -0700 |
| commit | 3486235338faa1377bb4e1a8981a45b4ee6edfa9 (patch) | |
| tree | 3b40a647ccbfd39e15baa824ae67c1281d100e86 /backends/verilog | |
| parent | 43081337fa4a85cd4a1a007576eaf945816bd576 (diff) | |
| download | yosys-3486235338faa1377bb4e1a8981a45b4ee6edfa9.tar.gz yosys-3486235338faa1377bb4e1a8981a45b4ee6edfa9.tar.bz2 yosys-3486235338faa1377bb4e1a8981a45b4ee6edfa9.zip | |
Make liberal use of IdString.in()
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 776f4eacb..9a797b535 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -949,7 +949,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffe") + if (cell->type.in("$dff", "$adff", "$dffe")) { RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst; bool pol_clk, pol_arst = false, pol_en = false; |