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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 12:20:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 12:20:08 -0700 |
| commit | 6d77236f3845cd8785e7bdd4da3c5ef966be6043 (patch) | |
| tree | 9a55ec79ecd07e4077dbb90634be19e168b15e48 /backends/verilog | |
| parent | 71eff6f0deae3ffaf75cca22768b66a2dc918b3e (diff) | |
| download | yosys-6d77236f3845cd8785e7bdd4da3c5ef966be6043.tar.gz yosys-6d77236f3845cd8785e7bdd4da3c5ef966be6043.tar.bz2 yosys-6d77236f3845cd8785e7bdd4da3c5ef966be6043.zip | |
substr() -> compare()
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6065a71ff..7b1db4776 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -604,7 +604,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.substr(0, 6) == "$_DFF_") + if (cell->type.begins_with("$_DFF_")) { std::string reg_name = cellname(cell); bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); @@ -645,7 +645,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.substr(0, 8) == "$_DFFSR_") + if (cell->type.begins_with("$_DFFSR_")) { char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; |