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* ABC9: Cell Port Bug Patch (#3670)Benjamin Barzen2023-04-221-1/+5
| | | | | | | | | | | | | | | | | * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* sim: Improvements and fixes for yw cosimJannis Harder2023-01-111-12/+1
| | | | | | * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output
* aiger: Use new JSON code for writing aiger witness map filesJannis Harder2023-01-111-49/+49
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* write_aiger: Fix non-$_FF_ FFsJannis Harder2022-08-181-1/+1
| | | | This broke while switching sby's formal flows to always use $_FF_'s.
* aiger: Add yosys-witness supportJannis Harder2022-08-161-0/+169
| | | | | Adds a new json based aiger map file and yosys-witness converters to us this to convert between native and AIGER witness files.
* aiger: Support $anyinit cellsJannis Harder2022-08-161-0/+11
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* Add -no-startoffset option to write_aigerMiodrag Milanovic2022-03-251-8/+17
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* sta: very crude static timing analysis passLofty2021-11-251-15/+16
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-082-2/+2
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-291-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* Replace assert in xaiger with more useful error messageDan Ravensloft2021-03-101-1/+2
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* use the new isPublic() in a few placesN. Engelhardt2020-09-142-2/+2
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* Use C++11 final/override keywords.whitequark2020-06-182-4/+4
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* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-28/+22
|\ | | | | abc9: -dff improvements
| * xaiger: cleanupEddie Hung2020-05-251-28/+22
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* | xaiger: promote abc9_keep wiresEddie Hung2020-05-251-1/+1
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* xaiger: do not derive cellsEddie Hung2020-05-241-7/+1
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* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-141-5/+5
| | | | instead of moving them to $__ prefix
* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-141-40/+32
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-141-18/+20
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* xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarityEddie Hung2020-05-141-16/+5
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* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-141-0/+1
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* Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"Eddie Hung2020-05-141-4/+0
| | | | | This reverts commit 759283fa65b1195ebe3a5bc6890ec622febca0eb, reversing changes made to f41c7ccfff4bf104c646ca4b85e079a0f91c9151.
* xaiger: always sort input/output bits by port idEddie Hung2020-05-141-12/+10
| | | | redundant for normal design, but necessary for holes
* abc9: generate $abc9_holes design instead of <name>$holesEddie Hung2020-05-141-3/+9
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* aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-141-6/+10
| | | | Since abc9 doesn't like negative mergeability values
* xaiger: update help textEddie Hung2020-05-141-4/+4
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* xaiger: do not treat (* init=1'bx *) as 1'b0Eddie Hung2020-05-141-1/+1
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* xaiger: when -dff use (* init *) for initial stateEddie Hung2020-05-141-3/+15
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-8/+2
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* xaiger: output $_DFF_[NP]_ with mergeability if -dff optionEddie Hung2020-05-141-42/+44
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* aiger: fixes for ports that have start_offset != 0Eddie Hung2020-05-022-9/+8
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* xaiger: add check for $__ABC9_DELAY modelEddie Hung2020-04-131-0/+4
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-36/+36
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* kernel: use more ID::*Eddie Hung2020-04-022-17/+17
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* xaiger: remove some unnecessary operations ...Eddie Hung2020-03-061-9/+2
| | | | | ... since they can not be triggered by (* keep *) anymore (but could still be triggered by (* abc9_scc *) !?!)
* abc9: (* keep *) wires to be PO only, not PI as well; fix scc handlingEddie Hung2020-03-061-3/+4
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* Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-1/+1
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* write_xaiger: add comment about arrival times of flop outputsEddie Hung2020-02-271-0/+1
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* Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-29/+15
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* abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-38/+44
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* xilinx: improve specify functionalityEddie Hung2020-02-271-0/+3
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* Revert "abc9: fix abc9_arrival for flops"Eddie Hung2020-02-141-5/+2
| | | | This reverts commit f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.
* write_xaiger: default value for abc9_initEddie Hung2020-02-131-1/+1
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* abc9: fix abc9_arrival for flopsEddie Hung2020-02-131-2/+5
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* Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-271-3/+3
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| * write_xaiger: fix for (* keep *) on flop outputEddie Hung2020-01-211-3/+3
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* | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+2
|\| | | | | | | eddie/abc9_required
| * write_xaiger: skip abc9_flop only if abc_box_seq presentEddie Hung2020-01-151-1/+2
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* | abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)Eddie Hung2020-01-141-1/+1
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