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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:08:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 722540dbf942d2b8acbaf7372001c7d982eb2845 (patch) | |
| tree | b852f01139a2a9f8b59ffeddfb8edd33a7272557 /backends/aiger | |
| parent | 5ad3a8528896a2e2539f2de98194eb0a6cce36c9 (diff) | |
| download | yosys-722540dbf942d2b8acbaf7372001c7d982eb2845.tar.gz yosys-722540dbf942d2b8acbaf7372001c7d982eb2845.tar.bz2 yosys-722540dbf942d2b8acbaf7372001c7d982eb2845.zip | |
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ddda1bd5a..abb9ae30f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -644,6 +644,7 @@ struct XAigerWriter SigBit Q = sigmap(cell->getPort(ID::Q)); State init = init_map.at(Q, State::Sx); + log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init)); if (init == State::S1) write_s_buffer(1); else if (init == State::S0) |