| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | Spelling fixes | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
| | | |/ / | |/| | | ||||||
| | * | | | Add default entry to testcase | Eddie Hung | 2019-04-11 | 1 | -2/+3 | |
| | * | | | Recognise default entry in case even if all cases covered (#931) | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
| | |/ / | ||||||
| | * | | Fix a few typos | Eddie Hung | 2019-04-08 | 1 | -3/+3 | |
| * | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| * | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
| * | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
| * | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
| * | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 | |
| * | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| |\ \ \ | | |/ | |/| | ||||||
| | * | | Add non-input bits driven by unrecognised cells as ci_bits | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| * | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
| * | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
| * | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
| * | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 | |
| * | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -24/+21 | |
| |\| | | ||||||
| | * | | parse_aiger() to rename all $lut cells after "clean" | Eddie Hung | 2019-04-10 | 1 | -24/+21 | |
| * | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 | |
| * | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
| * | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 | |
| * | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
| * | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 | |
| * | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 | |
| * | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 | |
| * | | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 | |
| * | | | Add "-lut <file>" support to abc9 | Eddie Hung | 2019-04-09 | 1 | -13/+31 | |
| * | | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 | |
| * | | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 | |
| * | | | Add "-box" option to abc9 | Eddie Hung | 2019-04-09 | 1 | -7/+22 | |
| * | | | Add 'setundef -zero' call prior to aigmap in abc9 | Eddie Hung | 2019-04-09 | 1 | -0/+4 | |
| * | | | Comment out | Eddie Hung | 2019-04-09 | 1 | -1/+1 | |
| * | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 2 | -1/+14 | |
| |/ / | ||||||
| * | | More space fixing | Eddie Hung | 2019-04-08 | 1 | -2/+2 | |
| * | | Fix spacing | Eddie Hung | 2019-04-08 | 1 | -29/+29 | |
| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 115 | -710/+5842 | |
| |\| | ||||||
| | * | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 | |
| | |\ | ||||||
| | | * | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 | |
| | |/ | ||||||
| | * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 | |
| | * | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 | |
| | * | Merge pull request #913 from smunaut/fix_proc_mux | Eddie Hung | 2019-04-03 | 1 | -1/+1 | |
| | |\ | ||||||
| | | * | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | Sylvain Munaut | 2019-04-03 | 1 | -1/+1 | |
| | |/ | ||||||
| | * | Merge pull request #912 from YosysHQ/bram_addr_en | Clifford Wolf | 2019-04-03 | 1 | -0/+2 | |
| | |\ | ||||||
| | | * | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 | |
| | * | | Merge pull request #910 from ucb-bar/memupdates | Clifford Wolf | 2019-04-03 | 1 | -30/+173 | |
| | |\ \ | | |/ | |/| | ||||||
| | | * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 | |
| | * | | Merge pull request #895 from YosysHQ/pmux2shiftx | Eddie Hung | 2019-04-02 | 1 | -0/+28 | |
| | |\ \ | | |/ | |/| | ||||||
| | | * | Create one $shiftx per bit in width | Eddie Hung | 2019-03-25 | 1 | -10/+17 | |
| | | * | Add a pmux-to-shiftx optimisation to proc_mux | Eddie Hung | 2019-03-23 | 1 | -0/+21 | |
| | * | | Merge pull request #907 from YosysHQ/clifford/fix906 | Clifford Wolf | 2019-03-30 | 1 | -0/+2 | |
| | |\ \ | ||||||
| | | * | | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 | |
| | |/ / | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |