| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove .0 from clang-8.0 | Eddie Hung | 2019-08-23 | 1 | -2/+2 |
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| * | Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! | Eddie Hung | 2019-08-23 | 1 | -3/+5 |
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| * | bionic -> xenial as its on whitelist | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| * | Bump gcc from 4.8 to 4.9 as undefined reference | Eddie Hung | 2019-08-23 | 1 | -35/+7 |
| | | | | | | ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0 | ||||
| * | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 |
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| * | do not require boost if pyosys is not used | Miodrag Milanovic | 2019-08-22 | 1 | -0/+2 |
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| * | require tcl-tk in Brewfile | Chris Shucksmith | 2019-08-22 | 1 | -0/+1 |
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| * | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Visual Studio build fix | Miodrag Milanovic | 2019-08-02 | 1 | -0/+1 |
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| * | Fix linking issue for new mxe and pthread | Miodrag Milanovic | 2019-08-02 | 1 | -1/+2 |
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| * | Fix yosys linking for mxe | Miodrag Milanovic | 2019-08-02 | 1 | -1/+1 |
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| * | New mxe hacks needed to support 2ca237e | Miodrag Milanovic | 2019-08-02 | 1 | -0/+4 |
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| * | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-02 | 8 | -17/+20 |
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| * | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -10/+101 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 |
| | | | | write_verilog: fix placement of case attributes | ||||
| * | Update CHANGELOG | David Shah | 2019-07-09 | 1 | -0/+1 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -16/+28 |
| | | | | More support for case rule attributes | ||||
| * | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 3 | -5/+15 |
| | | | | Allow attributes on individual switch cases in RTLIL | ||||
| * | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire | Clifford Wolf | 2019-07-09 | 1 | -0/+3 |
| | | | | Throw runtime exception when trying to convert inexistend C++ object to Python | ||||
| * | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-09 | 3 | -82/+26 |
| | | | | Improve specify dummy parser | ||||
| * | Merge pull request #1154 from whitequark/manual-sync-always | Clifford Wolf | 2019-07-09 | 1 | -2/+3 |
| | | | | manual: explain the purpose of `sync always` | ||||
| * | Merge pull request #1153 from YosysHQ/dave/fix_multi_mux | David Shah | 2019-07-09 | 3 | -3/+25 |
| | | | | memory_dff: Fix checking of feedback mux input when more than one mux | ||||
| * | Fix read_verilog assert/assume/etc on default case label, fixes ↵ | Clifford Wolf | 2019-07-09 | 1 | -0/+2 |
| | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-07-09 | 1 | -1/+1 |
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| * | Merge pull request #1146 from gsomlo/gls-test-abc-ext | Clifford Wolf | 2019-07-09 | 4 | -8/+29 |
| | | | | tests: use optional ABCEXTERNAL when specified | ||||
| * | Checkout yosys-0.9-rc branch of yosys-tests | Eddie Hung | 2019-07-02 | 1 | -1/+1 |
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| * | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 |
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| * | Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
| |\ | | | | | tests: Check that Icarus can parse arch sim models | ||||
| | * | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 |
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| | * | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 2 | -0/+9 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Grr | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
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| * | | Capitalisation | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
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| * | | Make CHANGELOG clearer | Eddie Hung | 2019-06-27 | 1 | -0/+1 |
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| * | | Merge pull request #1143 from YosysHQ/clifford/fix1135 | Eddie Hung | 2019-06-27 | 4 | -8/+38 |
| |\ \ | | | | | | | Add "pmux2shiftx -norange" | ||||
| | * | | Add #1135 testcase | Eddie Hung | 2019-06-27 | 2 | -5/+26 |
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| | * | | Add "pmux2shiftx -norange", fixes #1135 | Clifford Wolf | 2019-06-27 | 2 | -3/+12 |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | synth_xilinx -arch -> -family, consistent with older synth_intel | Eddie Hung | 2019-06-27 | 1 | -7/+8 |
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| * | | Merge pull request #1142 from YosysHQ/clifford/fix1132 | Eddie Hung | 2019-06-27 | 2 | -6/+345 |
| |\ \ | | | | | | | Fix handling of partial covers in muxcover | ||||
| | * | | Copy tests from eddie/fix1132 | Eddie Hung | 2019-06-27 | 1 | -0/+320 |
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| | * | | Fix handling of partial covers in muxcover, fixes #1132 | Clifford Wolf | 2019-06-27 | 1 | -6/+25 |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux | Eddie Hung | 2019-06-27 | 2 | -12/+34 |
| |\ \ | |/ |/| | synth_xilinx: Add -nocarry and -nowidelut options | ||||
| | * | Grrr | Eddie Hung | 2019-06-26 | 1 | -2/+2 |
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| | * | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -5/+5 |
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| | * | Oops. Actually use nocarry flag as spotted by @koriakin | Eddie Hung | 2019-06-26 | 1 | -5/+7 |
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| | * | synth_ecp5 rename -nomux to -nowidelut, but preserve former | Eddie Hung | 2019-06-26 | 1 | -6/+6 |
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| | * | Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into ↵ | Eddie Hung | 2019-06-26 | 1 | -4/+24 |
| | |\ | | | | | | | | | | koriakin/xc7nocarrymux | ||||
| | | * | synth_xilinx: Add -nocarry and -nomux options. | Marcin Kościelnicki | 2019-04-30 | 1 | -7/+26 |
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| * | | | Merge pull request #1137 from mmicko/cell_sim_fix | Clifford Wolf | 2019-06-26 | 2 | -14/+1 |
| |\ \ \ | | | | | | | | | Simulation model verilog fix | ||||
| | * | | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 2 | -14/+1 |
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| * | | | Improve opt_clean handling of unused public wires | Clifford Wolf | 2019-06-26 | 1 | -2/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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