iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Remove .0 from clang-8.0	Eddie Hung	2019-08-23	1	-2/+2
*	Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!	Eddie Hung	2019-08-23	1	-3/+5
*	bionic -> xenial as its on whitelist	Eddie Hung	2019-08-23	1	-1/+1
*	Bump gcc from 4.8 to 4.9 as undefined reference	Eddie Hung	2019-08-23	1	-35/+7
*	Make macOS depenency clear	Miodrag Milanovic	2019-08-23	1	-2/+5
*	do not require boost if pyosys is not used	Miodrag Milanovic	2019-08-22	1	-0/+2
*	require tcl-tk in Brewfile	Chris Shucksmith	2019-08-22	1	-0/+1
*	Bump year in copyright notice	Clifford Wolf	2019-08-22	3	-3/+3
*	Visual Studio build fix	Miodrag Milanovic	2019-08-02	1	-0/+1
*	Fix linking issue for new mxe and pthread	Miodrag Milanovic	2019-08-02	1	-1/+2
*	Fix yosys linking for mxe	Miodrag Milanovic	2019-08-02	1	-1/+1
*	New mxe hacks needed to support 2ca237e	Miodrag Milanovic	2019-08-02	1	-0/+4
*	Fix formatting for msys2 mingw build using GetSize	Miodrag Milanovic	2019-08-02	8	-17/+20
*	Update CHANGELOG	David Shah	2019-07-26	1	-10/+101
*	Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position	Clifford Wolf	2019-07-09	1	-3/+2
*	Update CHANGELOG	David Shah	2019-07-09	1	-0/+1
*	Merge pull request #1163 from whitequark/more-case-attrs	Clifford Wolf	2019-07-09	3	-16/+28
*	Merge pull request #1162 from whitequark/rtlil-case-attrs	Clifford Wolf	2019-07-09	3	-5/+15
*	Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire	Clifford Wolf	2019-07-09	1	-0/+3
*	Merge pull request #1147 from YosysHQ/clifford/fix1144	Clifford Wolf	2019-07-09	3	-82/+26
*	Merge pull request #1154 from whitequark/manual-sync-always	Clifford Wolf	2019-07-09	1	-2/+3
*	Merge pull request #1153 from YosysHQ/dave/fix_multi_mux	David Shah	2019-07-09	3	-3/+25
*	Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...	Clifford Wolf	2019-07-09	1	-0/+2
*	autotest.sh to define _AUTOTB when test_autotb	Eddie Hung	2019-07-09	1	-1/+1
*	Merge pull request #1146 from gsomlo/gls-test-abc-ext	Clifford Wolf	2019-07-09	4	-8/+29
*	Checkout yosys-0.9-rc branch of yosys-tests	Eddie Hung	2019-07-02	1	-1/+1
*	Add missing CHANGELOG entries	Eddie Hung	2019-06-28	1	-0/+3
*	Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog	Eddie Hung	2019-06-27	2	-0/+19
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\| *	Add simcells.v, simlib.v, and some output	Eddie Hung	2019-06-27	1	-1/+11
\| *	tests: Check that Icarus can parse arch sim models	David Shah	2019-06-26	2	-0/+9
* \|	Grr	Eddie Hung	2019-06-27	1	-1/+1
* \|	Capitalisation	Eddie Hung	2019-06-27	1	-1/+1
* \|	Make CHANGELOG clearer	Eddie Hung	2019-06-27	1	-0/+1
* \|	Merge pull request #1143 from YosysHQ/clifford/fix1135	Eddie Hung	2019-06-27	4	-8/+38
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\| * \|	Add #1135 testcase	Eddie Hung	2019-06-27	2	-5/+26
\| * \|	Add "pmux2shiftx -norange", fixes #1135	Clifford Wolf	2019-06-27	2	-3/+12
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* \|	synth_xilinx -arch -> -family, consistent with older synth_intel	Eddie Hung	2019-06-27	1	-7/+8
* \|	Merge pull request #1142 from YosysHQ/clifford/fix1132	Eddie Hung	2019-06-27	2	-6/+345
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\| * \|	Copy tests from eddie/fix1132	Eddie Hung	2019-06-27	1	-0/+320
\| * \|	Fix handling of partial covers in muxcover, fixes #1132	Clifford Wolf	2019-06-27	1	-6/+25
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* \|	Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux	Eddie Hung	2019-06-27	2	-12/+34
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\| *	Grrr	Eddie Hung	2019-06-26	1	-2/+2
\| *	Fix spacing	Eddie Hung	2019-06-26	1	-5/+5
\| *	Oops. Actually use nocarry flag as spotted by @koriakin	Eddie Hung	2019-06-26	1	-5/+7
\| *	synth_ecp5 rename -nomux to -nowidelut, but preserve former	Eddie Hung	2019-06-26	1	-6/+6
\| *	Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...	Eddie Hung	2019-06-26	1	-4/+24
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\| \| *	synth_xilinx: Add -nocarry and -nomux options.	Marcin Kościelnicki	2019-04-30	1	-7/+26
* \| \|	Merge pull request #1137 from mmicko/cell_sim_fix	Clifford Wolf	2019-06-26	2	-14/+1
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\| * \| \|	Simulation model verilog fix	Miodrag Milanovic	2019-06-26	2	-14/+1
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* \| \|	Improve opt_clean handling of unused public wires	Clifford Wolf	2019-06-26	1	-2/+2